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MC9S08SH4 Datasheet(PDF) 76 Page - Freescale Semiconductor, Inc |
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MC9S08SH4 Datasheet(HTML) 76 Page - Freescale Semiconductor, Inc |
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76 / 341 page  Chapter 5 Resets, Interrupts, and General System Control MC9S08SH8 MCU Series Data Sheet, Rev. 3 72 Freescale Semiconductor 5.7.7 System Power Management Status and Control 1 Register (SPMSC1) This high page register contains status and control bits to support the low voltage detect function, and to enable the bandgap voltage reference for use by the ADC module. Figure 5-9. System Power Management Status and Control 1 Register (SPMSC1) 76543210 R LVWF1 1 LVWF will be set in the case when V Supply transitions below the trip point or after reset and VSupply is already below VLVW 0 LVWIE LVDRE LVDSE LVDE 0 BGBE W LVWACK Reset: 00011100 = Unimplemented or Reserved Table 5-10. SPMSC1 Register Field Descriptions Field Description 7 LVWF Low-Voltage Warning Flag — The LVWF bit indicates the low voltage warning status. 0 Low voltage warning is not present. 1 Low voltage warning is present or was present. 6 LVWACK Low-Voltage Warning Acknowledge — The LVWF bit indicates the low voltage warning status.Writing a 1 to LVWACK clears LVWF to a 0 if a low voltage warning is not present. 5 LVWIE Low-Voltage Warning Interrupt Enable — This bit enables hardware interrupt requests for LVWF. 0 Hardware interrupt disabled (use polling). 1 Request a hardware interrupt when LVWF = 1. 4 LVDRE Low-Voltage Detect Reset Enable — This write-once bit enables LVD events to generate a hardware reset (provided LVDE = 1). 0 LVD events do not generate hardware resets. 1 Force an MCU reset when an enabled low-voltage detect event occurs. 3 LVDSE Low-Voltage Detect Stop Enable — Provided LVDE = 1, this control bit determines whether the low-voltage detect function operates when the MCU is in stop mode. 0 Low-voltage detect disabled during stop mode. 1 Low-voltage detect enabled during stop mode. 2 LVDE Low-Voltage Detect Enable — This write-once bit enables low-voltage detect logic and qualifies the operation of other bits in this register. 0 LVD logic disabled. 1 LVD logic enabled. 0 BGBE Bandgap Buffer Enable — This bit enables an internal buffer for the bandgap voltage reference for use by the ADC module on one of its internal channels or ACMP on its ACMP+ input. 0 Bandgap buffer disabled. 1 Bandgap buffer enabled. |
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