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MC9S08SH4 Datasheet(PDF) 71 Page - Freescale Semiconductor, Inc |
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MC9S08SH4 Datasheet(HTML) 71 Page - Freescale Semiconductor, Inc |
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71 / 341 page  Chapter 5 Resets, Interrupts, and General System Control MC9S08SH8 MCU Series Data Sheet, Rev. 3 Freescale Semiconductor 67 5.7.2 System Reset Status Register (SRS) This high page register includes read-only status flags to indicate the source of the most recent reset. When a debug host forces reset by writing 1 to BDFR in the SBDFR register, none of the status bits in SRS will be set. Writing any value to this register address causes a COP reset when the COP is enabled except the values 0x55 and 0xAA. Writing a 0x55-0xAA sequence to this address clears the COP watchdog timer without affecting the contents of this register. The reset state of these bits depends on what caused the MCU to reset. Figure 5-3. System Reset Status (SRS) 76543210 R POR PIN COP ILOP ILAD 0 LVD 0 W Writing 0x55, 0xAA to SRS address clears COP watchdog timer. POR: 10000010 LVR: u(1) 1 u = unaffected 0000010 Any other reset: 0 Note(2) 2 Any of these reset sources that are active at the time of reset entry will cause the corresponding bit(s) to be set; bits corresponding to sources that are not active at the time of reset entry will be cleared. Note(2) Note(2) Note(2) 000 Table 5-4. SRS Register Field Descriptions Field Description 7 POR Power-On Reset — Reset was caused by the power-on detection logic. Because the internal supply voltage was ramping up at the time, the low-voltage reset (LVD) status bit is also set to indicate that the reset occurred while the internal supply was below the LVD threshold. 0 Reset not caused by POR. 1 POR caused reset. 6 PIN External Reset Pin — Reset was caused by an active-low level on the external reset pin. 0 Reset not caused by external reset pin. 1 Reset came from external reset pin. 5 COP Computer Operating Properly (COP) Watchdog — Reset was caused by the COP watchdog timer timing out. This reset source can be blocked by COPT bits = 0:0.. 0 Reset not caused by COP timeout. 1 Reset caused by COP timeout. 4 ILOP Illegal Opcode — Reset was caused by an attempt to execute an unimplemented or illegal opcode. The STOP instruction is considered illegal if stop is disabled by STOPE = 0 in the SOPT register. The BGND instruction is considered illegal if active background mode is disabled by ENBDM = 0 in the BDCSC register. 0 Reset not caused by an illegal opcode. 1 Reset caused by an illegal opcode. |
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