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DSPB56364AF100 Datasheet(PDF) 70 Page - Freescale Semiconductor, Inc |
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DSPB56364AF100 Datasheet(HTML) 70 Page - Freescale Semiconductor, Inc |
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70 / 148 page  JTAG Timing DSP56364 Technical Data, Rev. 4.1 3-54 Freescale Semiconductor Figure 3-28 Test Clock Input Timing Diagram Figure 3-29 Boundary Scan (JTAG) Timing Diagram 509 TMS, TDI data hold time 25.0 — ns 510 TCK low to TDO data valid 0.0 44.0 ns 511 TCK low to TDO high impedance 0.0 44.0 ns 1 V CC = 3.3 V ± 0.16 V; TJ = 0°C to +105°C, CL = 50 pF 2 All timings apply to OnCE module data transfers because it uses the JTAG port as an interface. Table 3-22 JTAG Timing1. 2 (continued) No. Characteristics All Frequencies Unit Min Max TCK (Input) VM VM VIH VIL 501 502 502 503 503 AA0496 TCK (Input) Data Inputs Data Outputs Data Outputs Data Outputs VIH VIL Input Data Valid Output Data Valid Output Data Valid 505 504 506 507 506 AA0497 |
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