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MT46V32M16 Datasheet(PDF) 16 Page - Micron Technology |
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MT46V32M16 Datasheet(HTML) 16 Page - Micron Technology |
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16 / 93 page  PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a Micron Technology, Inc., reserves the right to change products or specifications without notice. 512Mb_DDR_x4x8x16_D2.fm - 512Mb DDR: Rev. Q; Core DDR Rev. E 7/11 EN 16 ©2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM Electrical Specifications – IDD Table 7: IDD Specifications and Conditions (x16) Die Revision F Only VDDQ = 2.6V ±0.1V, VDD = 2.6V ±0.1V (-5B); VDDQ = 2.5V ±0.2V, VDD = 2.5V ±0.2V (-6, -6T, -75E, -75Z, -75); 0°C d TA d 70°C; Notes: 1–5, 11, 13, 15, 47; Notes appear on pages 37–42; See also Table 10 on page 20 Parameter/Condition Symbol -5B -6/6T -75E -75Z/-75 Units Notes Operating one-bank active-precharge current: tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles IDD0 155 130 130 115 mA 23, 48 Operating one-bank active-read-precharge current: Burst = 4; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle IDD1 195 160 160 145 mA 23, 48 Precharge power-down standby current: All banks idle; Power-down mode; tCK = tCK (MIN); CKE = (LOW) IDD2P 5 5 5 5 mA 24, 33 Idle standby current: CS# = HIGH; All banks are idle; tCK = tCK (MIN); CKE = HIGH; Address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DQS, and DM IDD2F 55 45 45 40 mA 51 Active power-down standby current: One bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW IDD3P 45 35 35 30 mA 24, 33 Active standby current: CS# = HIGH; CKE = HIGH; One bank active ; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle IDD3N 60 50 50 45 mA 23 Operating burst read current: Burst = 2; Continuous burst reads; One bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA IDD4R 210 165 165 145 mA 23, 48 Operating burst write current: Burst = 2; Continuous burst writes; One bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle IDD4W 215 195 160 135 mA 23 Auto refresh burst current: tRFC = tRFC (MIN) IDD5 345 290 290 280 mA 50 tRFC = 7.8µs IDD5A 11 10 10 10 mA 28, 50 tRFC = 1.95µs IDD5A 16 15 15 15 mA 28, 50 Self refresh current: CKE d 0.2V Standard IDD6 65 5 5 mA 12 Low power (L) IDD6A 43 3 3 mA 12 Operating bank interleave read current: Four bank interleaving READs (burst = 4) with auto precharge, tRC = minimum tRC allowed; tCK = tCK (MIN); Address and control inputs change only during active READ or WRITE commands IDD7 480 405 400 350 mA 23, 49 |
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