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MT46V32M16 Datasheet(PDF) 56 Page - Micron Technology |
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MT46V32M16 Datasheet(HTML) 56 Page - Micron Technology |
56 / 93 page PDF: 09005aef80768abb/Source: 09005aef82a95a3a Micron Technology, Inc., reserves the right to change products or specifications without notice. DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. Q; Core DDR Rev. E 7/11 EN 56 ©2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 DDR SDRAM Operations Figure 23: INITIALIZATION Timing Diagram Notes: 1. VTT is not applied directly to the device; however, tVTD t 0 to avoid device latch-up. VDDQ, VTT, and VREF d VDD + 0.3V. Alternatively, VTT may be 1.35V maximum during power-up, even if VDD/VDDQ are 0V, provided a minimum of 42: of series resistance is used between the VTT supply and the input pin. Once initialized, VREF must always be powered within the specified range. 2. Although not required by the Micron device, JEDEC specifies issuing another LMR command (A8 = 0) prior to activating any bank. If another LMR command is issued, the same, previ- ously issued operating parameters must be used. 3. The two AUTO REFRESH commands at Td0 and Te0 may be applied following the LMR com- mand at Ta0. 4. tMRD is required before any command can be applied (during MRD time only NOPs or DESELECTs are allowed), and 200 cycles of CK are required before a READ command can be issued. 5. While programming the operating parameters, reset the DLL with A8 = 1. tVTD1 CKE LVCMOS LOW level DQ BA0, BA1 200 cycles of CK4 Load extended mode register Load mode register5 tMRD tMRD tRP tRFC tRFC tIS Power-up: VDD and CK stable T = 200µs High-Z tIH DM DQS High-Z Address RA A10 All banks CK CK# tCH tCL tCK VTT1 VREF VDD VDDQ Command LMR NOP PRE LMR AR AR ACT2 tIS tIH BA0 = 1 BA1 = 0 tIS tIH tIS tIH BA0 = 0 BA1 = 0 tIS tIH ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) Code Code tIS tIH Code Code3 PRE All banks tIS tIH T0 T1 Ta0 Tb0 Tc0 Td0 Te0 Tf0 ( ) ( ) Don’t Care BA ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) tRP ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) RA Indicates A Break in Time Scale |
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