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GTLP16617 Datasheet(PDF) 2 Page - Fairchild Semiconductor

Part No. GTLP16617
Description  17-Bit TTL/GTLP Synchronous Bus Transceiver with Buffered Clock
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Maker  FAIRCHILD [Fairchild Semiconductor]
Homepage  http://www.fairchildsemi.com
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GTLP16617 Datasheet(HTML) 2 Page - Fairchild Semiconductor

 
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Pin Descriptions
Connection Diagram
Functional Description
The GTLP16617 is a 17 bit registered transceiver containing D-type flip-flop, latch and transparent modes of operation for
the data path and a GTLP translation of the CLKAB signal (CLKOUT). Data flow in each direction is controlled by the clock
enables (CEAB and CEBA), latch enables (LEAB and LEBA), clock (CLKAB and CLKBA) and output enables (OEAB and
OEBA). The clock enables (CEAB and CEBA) enable all 17 data bits. The output enables (OEAB and OEBA) control both
the 17 bits of data and the CLKOUT/CLKIN buffered clock paths and the OEAB is synchronous with the CLKAB signal. The
OEBA can not be synchronous since we are passing the clock through the device with data and we would need to generate
the CLKBA signal elsewhere. It should also be noted that the OEAB register is controlled by CLKAB only, and is also not
inhibited by the CEAB signal.
For A-to-B data flow, when CEAB is LOW, the device operates on the LOW-to-HIGH transition of CLKAB for the flip-flop
and on the HIGH-to-LOW transition of LEAB for the latch path. That is, if CEAB is LOW and LEAB is LOW the A data is
latched regardless as to the state of CLKAB (HIGH or LOW) and if LEAB is HIGH the device is in transparent mode. When
OEAB is registered LOW the outputs are active. When OEAB is registered HIGH the outputs are HIGH impedance. The
data flow of B-to-A is similar except that CEBA, OEBA, LEBA and CLKBA are used.
Truth Table
(Note 1)
Note 1: A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, CLKBA, CEBA.
Note 2: LH edge on CLKAB is required when changing the input on OEAB pin.
Note 3: OEAB met set-up time prior to CLKAB LH transition
Note 4: Output level before the indicated steady state input conditions were established, provided CLKAB was HIGH prior to LEAB going LOW.
Note 5: Output level before the indicated steady state input conditions were established.
Pin Names
Description
OEAB
A-to-B Output Enable (Active LOW)
OEBA
B-to-A Output Enable (Active LOW)
CEAB
A-to-B Clock Enable (Active LOW)
CEBA
B-to-A Clock Enable (Active LOW)
LEAB
A-to-B Latch Enable (Transparent HIGH)
LEBA
B-to-A Latch Enable (Transparent HIGH)
VREF
GTLP Reference Voltage
CLKAB
A-to-B Clock
CLKBA
B-to-A Clock
A1-A17
A-to-B Data Inputs or B-to-A 3-STATE
Data Outputs
B1-B17
B-to-A Data Inputs or
A-to-B Open Drain Outputs
CLKIN
B-to-A Buffered Clock Output
CLKOUT
GTLP Buffered Clock Output of CLKAB
Inputs
Output
B
Mode
CEAB
OEAB(Note 2)
LEAB
CLKAB
A
XHX
X
Z (Note 3)
Latched storage of
A data
LL
L
H or L
X
B0(Note 4)
L
L
L
H or L
X
(Note 5)
X
L
H
X
L
L
Transparent
XL
H
X
H
H
LL
L
L
L
Clocked storage of
A data
LL
L
HH
HL
L
X
X
B0(Note 5)
Clock inhibit


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