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GTLP16617 Datasheet(PDF) 1 Page - Fairchild Semiconductor

Part No. GTLP16617
Description  17-Bit TTL/GTLP Synchronous Bus Transceiver with Buffered Clock
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Maker  FAIRCHILD [Fairchild Semiconductor]
Homepage  http://www.fairchildsemi.com

GTLP16617 Datasheet(HTML) 1 Page - Fairchild Semiconductor

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June 1997
Revised October 1998
© 1998 Fairchild Semiconductor Corporation
17-Bit TTL/GTLP Synchronous Bus Transceiver
with Buffered Clock
General Description
The GTLP16617 is a 17-bit registered synchronous bus
transceiver that provides TTL to GTLP signal level transla-
tion. It allows for transparent, latched and clocked modes
of data flow and provides a buffered GTLP (CLKOUT)
clock output from the TTL CLKAB. The device provides a
high speed interface between cards operating at TTL logic
levels and a backplane operating at GTLP logic levels.
High speed backplane operation is a direct result of
GTLP’s reduced output swing (
<1V), reduced input thresh-
old levels and output edge rate control. The edge rate con-
trol minimizes bus settling time. GTLP is a Fairchild
Semiconductor derivative of the Gunning Transceiver logic
(GTL) JEDEC standard JESD8-3.
Fairchild’s GTLP has internal edge-rate control and is pro-
cess, voltage, and temperature (PVT) compensated. Its
function is similar to BTL and GTL but with different output
levels and receiver threshold. GTLP output LOW level is
typically less than 0.5V, the output level HIGH is 1.5V and
the receiver threshold is 1.0V.
s Bidirectional interface between GTLP and TTL logic
s Edge Rate Control to minimize noise on the GTLP port
s Power up/down/off high impedance for live insertion.
s External VREF pin for receiver threshold
s CMOS technology for low power dissipation
s 5 V tolerant inputs and outputs on the A-Port
s Bus-hold data inputs on the A-Port eliminates the need
for external pull-up resistors on unused inputs.
s TTL compatible driver and control inputs
s Flow through pinout optimizes PCB layout
s Open drain on GTLP to support wired-or connection
s A-Port source/sink
−32 mA/+32 mA
s D-type flip-flop, latch and transparent data paths
s GTLP Buffered CLKAB signal available(CLKOUT)
s Recommended Operating Temperature
−40°C to 85°C
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Order Number
Package Number
Package Description
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118 0.300” Wide
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

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