Electronic Components Datasheet Search
  English  ▼

Delete All


Preview PDF Download HTML

GTLP16616 Datasheet(PDF) 1 Page - Fairchild Semiconductor

Part No. GTLP16616
Description  17-Bit TTL/GTLP Bus Transceiver with Buffered Clock
Download  10 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  FAIRCHILD [Fairchild Semiconductor]
Homepage  http://www.fairchildsemi.com

GTLP16616 Datasheet(HTML) 1 Page - Fairchild Semiconductor

Zoom Inzoom in Zoom Outzoom out
 1 / 10 page
background image
June 1997
Revised October 1998
© 1998 Fairchild Semiconductor Corporation
17-Bit TTL/GTLP Bus Transceiver
with Buffered Clock
General Description
The GTLP16616 is a 17-bit registered bus transceiver that
provides TTL to GTLP signal level translation. It allows for
transparent, latched and clocked modes of data flow and
provides a buffered GTLP (CLKOUT) clock output from the
TTL CLKAB. The device provides a high speed interface
between cards operating at TTL logic levels and a back-
plane operating at GTLP logic levels. High speed back-
plane operation is a direct result of GTLP’s reduced output
swing (
<1V), reduced input threshold levels and output
edge rate control. The edge rate control minimizes bus set-
tling time. GTLP is a Fairchild Semiconductor derivative of
the Gunning Transceiver logic (GTL) JEDEC standard
Fairchild’s GTLP has internal edge-rate control and is pro-
cess, voltage, and temperature (PVT) compensated. Its
function is similar to BTL and GTL but with different output
levels and receiver threshold. GTLP output LOW level is
typically less than 0.5V, the output level HIGH is 1.5V and
the receiver threshold is 1.0V.
s Bidirectional interface between GTLP and TTL logic
s Edge Rate Control to minimize noise on the GTLP port
s Power up/down/off high impedance for live insertion
s External VREF pin for receiver threshold
s CMOS technology for low power dissipation
s 5 V tolerant inputs and outputs on the A-Port
s Bus-hold data inputs on the A-Port eliminates the need
for external pull-up resistors on unused inputs.
s TTL compatible driver and control inputs
s Flow through pinout optimizes PCB layout
s Open drain on GTLP to support wired-or connection
s A-port source/sink
−32 mA/+32 mA
s D-type flip-flop, latch and transparent data paths
s GTLP Buffered CLKAB signal available (CLKOUT)
s Recommended Operating Temperature
−40°C to 85°C
Ordering Code:
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Order Number
Package Number
Package Description
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118 0.300” Wide
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Html Pages

1  2  3  4  5  6  7  8  9  10 

Datasheet Download

Link URL

Privacy Policy
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com

Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn