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AT29C040A-12JI Datasheet(PDF) 3 Page - ATMEL Corporation
ATMEL [ATMEL Corporation]
AT29C040A-12JI Datasheet(HTML) 3 Page - ATMEL Corporation
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SOFTWARE DATA PROTECTION:
A software controlled data protection feature is avail-
able on the AT29C040A. Once the software protection is enabled a software algorithm must
be issued to the device before a program may be performed. The software protection feature
may be enabled or disabled by the user; when shipped from Atmel, the software data protec-
tion feature is disabled. To enable the software data protection, a series of three program
commands to specific addresses with specific data must be performed. After the software data
protection is enabled the same three program commands must begin each program cycle in
order for the programs to occur. All software program commands must obey the sector pro-
gram timing specifications. The SDP feature protects all sectors, not just a single sector. Once
set, the software data protection feature remains active unless its disable command is issued.
Power transitions will not reset the software data protection feature, however the software fea-
ture will guard against inadvertent program cycles during power transitions.
After setting SDP, any attempt to write to the device without the three-byte command
sequence will start the internal write timers. No data will be written to the device; however, for
the duration of t
, a read operation will effectively be a polling operation.
After the software data protection’s 3-byte command code is given, a byte load is performed
by applying a low pulse on the WE or CE input with CE or WE low (respectively) and OE high.
The address is latched on the falling edge of CE or WE, whichever occurs last. The data is
latched by the first rising edge of CE or WE. The 256 bytes of data must be loaded into each
sector by the same procedure as outlined in the program section under device operation.
HARDWARE DATA PROTECTION:
Hardware features protect against inadvertent pro-
grams to the AT29C040A in the following ways: (a) V
sense – if V
is below 3.8V (typical),
the program function is inhibited; (b) V
power on delay – once V
has reached the V
sense level, the device will automatically time out 5 ms (typical) before programming; (c) Pro-
gram inhibit – holding any one of OE low, CE high or WE high inhibits program cycles; and (d)
Noise filter – pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a pro-
The product identification mode identifies the device and
manufacturer as Atmel. It may be accessed by hardware or software operation. The hardware
operation mode can be used by an external programmer to identify the correct programming
algorithm for the Atmel product. In addition, users may wish to use the software product identi-
fication mode to identify the part (i.e. using the device code), and have the system software
use the appropriate sector size for program operations. In this manner, the user can have a
common board design for 256K to 4-megabit densities and, with each density’ssector size in
a memory map, have the system software apply the appropriate sector size.
For details, see Operating Modes (for hardware operation) or Software Product Identification.
The manufacturer and device code is the same for both modes.
The AT29C040A features DATA polling to indicate the end of a program
cycle. During a program cycle an attempted read of the last byte loaded will result in the com-
plement of the loaded data on I/O7. Once the program cycle has been completed, true data is
valid on all outputs and the next cycle may begin. DATA polling may begin at any time during
the program cycle.
In addition to DATA polling the AT29C040A provides another method for
determining the end of a program or erase cycle. During a program or erase operation, suc-
cessive attempts to read data from the device will result in I/O6 toggling between one and
zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be
read. Examining the toggle bit may begin at any time during a program cycle.
OPTIONAL CHIP ERASE MODE:
The entire device can be erased by using a 6-byte soft-
ware code. Please see Software Chip Erase application note for details.
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