Electronic Components Datasheet Search
  English  ▼

Delete All


Preview PDF Download HTML

AD5173BRM2.5 Datasheet(PDF) 17 Page - Analog Devices

Part No. AD5173BRM2.5
Description  256-Position, One-Time Programmable, Dual-Channel, I2C Digital Potentiometers
Download  24 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD5173BRM2.5 Datasheet(HTML) 17 Page - Analog Devices

Back Button AD5173BRM2.5 Datasheet HTML 13Page - Analog Devices AD5173BRM2.5 Datasheet HTML 14Page - Analog Devices AD5173BRM2.5 Datasheet HTML 15Page - Analog Devices AD5173BRM2.5 Datasheet HTML 16Page - Analog Devices AD5173BRM2.5 Datasheet HTML 17Page - Analog Devices AD5173BRM2.5 Datasheet HTML 18Page - Analog Devices AD5173BRM2.5 Datasheet HTML 19Page - Analog Devices AD5173BRM2.5 Datasheet HTML 20Page - Analog Devices AD5173BRM2.5 Datasheet HTML 21Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 17 / 24 page
background image
Rev. H | Page 17 of 24
All digital inputs, SDA, SCL, AD0, and AD1, are protected with
a series input resistor and parallel Zener ESD structures, as
shown in Figure 43 and Figure 44.
Figure 43. ESD Protection of Digital Pins
A, B, W
Figure 44. ESD Protection of Resistor Terminals
The AD5172/AD5173 VDD to GND power supply defines the
boundary conditions for proper 3-terminal digital potenti-
ometer operation. Supply signals present on Terminal A,
Terminal B, and Terminal W that exceed VDD or GND are
clamped by the internal forward-biased diodes (see Figure 45).
Figure 45. Maximum Terminal Voltages Set by VDD and GND
Because the ESD protection diodes limit the voltage compliance
at Terminal A, Terminal B, and Terminal W (see Figure 45), it
is important to power VDD/GND before applying voltage to
Terminal A, Terminal B, and Terminal W. Otherwise, the diode
is forward-biased such that VDD is powered unintentionally and
may affect the rest of the user’s circuit. The ideal power-up
sequence is GND, VDD, digital inputs, and then VA/VB/VW. The
relative order of powering VA, VB, VW, and the digital inputs is
not important, as long as they are powered after VDD/GND.
To minimize the package pin count, both the one-time pro-
gramming and normal operating voltage supplies are applied to
the same VDD terminal of the device. The AD5172/AD5173
employ fuse link technology that requires 5.6 V to 5.8 V to blow
the internal fuses to achieve a given setting, but normal VDD can
be 2.7 V to 5.5 V. Such dual-voltage requirements need isolation
between the supplies if VDD is lower than the required VDD_OTP.
The fuse programming supply (either an on-board regulator or
rack-mount power supply) must be rated at 5.6 V to 5.8 V and
must be able to provide a 100 mA transient current for 400 ms
for successful one-time programming. When programming
is completed, the VDD_OTP supply must be removed to allow
normal operation at 2.7 V to 5.5 V; the device consumes only
microamps of current.
P1 = P2 = FDV302P, NDS0610
Figure 46. Isolate 5.7 V OTP Supply from 2.7 V Normal Operating Supply
For example, for those who operate their systems at 2.7 V, use of
the bidirectional, low threshold, P-channel MOSFETs is recom-
mended for the isolation of the supply. As shown in Figure 46,
this assumes that the 2.7 V system voltage is applied first and
that the P1 and P2 gates are pulled to ground, thus turning on
P1 and then P2. As a result, VDD of the AD5172/AD5173
approaches 2.7 V. When the AD5172/AD5173 setting is found,
the factory tester applies the VDD_OTP to both the VDD and the
MOSFET gates, thus turning P1 and P2 off. To program the
AD5172/AD5173 while the 2.7 V source is protected, execute
the OTP command at this time. When the OTP is completed,
the tester withdraws the VDD_OTP, and the setting of the AD5172
or AD5173 is fixed permanently.
The AD5172/AD5173 achieve the OTP function by blowing
internal fuses. Always apply the 5.6 V to 5.8 V one-time pro-
gram voltage requirement at the first fuse programming attempt.
Failure to comply with this requirement may lead to changing
the fuse structures, rendering programming inoperable.
Care should be taken when SCL and SDA are driven from a low
voltage logic controller. Users must ensure that the logic high
level is between 0.7 V × VDD and VDD + 0.5 V.
Poor PCB layout introduces parasitics that can affect fuse
programming. Therefore, it is recommended to add a 1 μF to
10 μF tantalum capacitor in parallel with a 1 nF ceramic capacitor
as close as possible to the VDD pin. The type and value chosen for
both capacitors are important. These capacitors work together to
provide both fast responsiveness and large supply current handling
with minimum supply droop during transients. As a result,
these capacitors increase the OTP programming success by not
inhibiting the proper energy needed to blow the internal fuses.
Additionally, C1 minimizes transient disturbance and low
frequency ripple, whereas C2 reduces high frequency noise
during normal operation.

Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24 

Datasheet Download

Go To PDF Page

Link URL

Privacy Policy
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com

Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn