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ADS1192IRSMR Datasheet(PDF) 28 Page - Texas Instruments |
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ADS1192IRSMR Datasheet(HTML) 28 Page - Texas Instruments |
28 / 67 page START Opcode START Pin DIN 4 / f CLK DRDY or t DR t SETTLE ADS1191 ADS1192 SBAS566A – DECEMBER 2011 – REVISED SEPTEMBER 2012 www.ti.com START The START pin must be set high or the START command sent to begin conversions. When START is low or if the START command has not been sent, the device does not issue a DRDY signal (conversions are halted). When using the START opcode to control conversion, hold the START pin low. The ADS1191/2 feature two modes to control conversion: continuous mode and single-shot mode. The mode is selected by SINGLE_SHOT (bit 7 of the CONFIG1 register). In multiple device configurations the START pin is used to synchronize devices (see the Multiple Device Configuration subsection of the SPI Interface section for more details). Settling Time The settling time (tSETTLE) is the time it takes for the converter to output fully settled data when the START signal is pulled high. Once START is pulled high, DRDY is also pulled high. The next falling edge of DRDY indicates that data are ready. Figure 32 shows the timing diagram and Table 5 shows the settling time for different data rates. The settling time depends on fCLK and the decimation ratio (controlled by the DR[2:0] bits in the CONFIG1 register). Table 4 shows the settling time as a function of tCLK. Note that when START is held high and there is a step change in the input signal, it takes 3 tDR for the filter to settle to the new value. Settled data are available on the fourth DRDY pulse. Settling time number uncertainty is one tMOD cycle. Therefore, it is recommended to add one tMOD cycle delay before issuing SCLK to retrieve data. (1) Settling time uncertainty is one tMOD cycle. Figure 32. Settling Time Table 5. Settling Time for Different Data Rates DR[2:0] SETTLING TIME(1) UNIT(2) 000 4100 tMOD 001 2052 tMOD 010 1028 tMOD 011 516 tMOD 100 260 tMOD 101 132 tMOD 110 68 tMOD 111 — — (1) Settling time uncertainty is one tMOD cycle. (2) tMOD = 4 tCLK for CLK_DIV = 0 and tMOD = 16 tCLK for CLK_DIV = 1. 28 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Links: ADS1191 ADS1192 |
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