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ADS1192IRSMR Datasheet(PDF) 24 Page - Texas Instruments

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Part # ADS1192IRSMR
Description  Two Low-Noise PGAs and Two High-Resolution ADCs (ADS1192)
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

ADS1192IRSMR Datasheet(HTML) 24 Page - Texas Instruments

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fCLK
fMOD
CLK_DIV
(Bit 6 of LOFF_STAT
Register)
Frequency
Divider
Divide-By-4
Frequency
Divider
Divide-By-16
ADS1191
ADS1192
SBAS566A – DECEMBER 2011 – REVISED SEPTEMBER 2012
www.ti.com
CLOCK
The ADS1191/2 provide two different methods for device clocking: internal and external. Internal clocking is
ideally suited for low-power, battery-powered systems. The internal oscillator is trimmed for accuracy at room
temperature. Over the specified temperature range the accuracy varies; see the Electrical Characteristics. Clock
selection is controlled by the CLKSEL pin and the CLK_EN register bit.
The CLKSEL pin selects either the internal or external clock. The CLK_EN bit in the CONFIG1 register enables
and disables the oscillator clock to be output in the CLK pin. A truth table for these two pins is shown in Table 3.
The CLK_EN bit is useful when multiple devices are used in a daisy-chain configuration. It is recommended that
during power-down the external clock be shut down to save power.
Table 3. CLKSEL Pin and CLK_EN Bit
CONFIG1.CLK_EN
CLKSEL PIN
BIT
CLOCK SOURCE
CLK PIN STATUS
0
X
External clock
Input: external clock
1
0
Internal clock oscillator
3-state
1
1
Internal clock oscillator
Output: internal clock oscillator
The ADS1191/2 have the option to choose between two different external clock frequencies (512 kHz or
2.048 MHz). This frequency is selected by setting the CLK_DIV bit (bit 6) in the LOFF_STAT register. The
modulator must be clocked at 128 kHz, regardless of the external clock frequency. Figure 28 shows the
relationship between the external clock (fCLK) and the modulator clock (fMOD). The default mode of operation is
fCLK = 512 kHz. The higher frequency option has only been provided to allow the SPI to run at a higher speed.
SCLK can be only twice the speed of fCLK during a register read and/or write.
Figure 28. Relationship Between External Clock (fCLK) and Modulator Clock (fMOD)
24
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Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Links: ADS1191 ADS1192


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