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ADS1192IRSMR Datasheet(PDF) 31 Page - Texas Instruments

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Part # ADS1192IRSMR
Description  Two Low-Noise PGAs and Two High-Resolution ADCs (ADS1192)
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

ADS1192IRSMR Datasheet(HTML) 31 Page - Texas Instruments

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START
DRDY
CS
SCLK
DIN
DOUT
Device 2
START
DRDY
CS
SCLK
DIN
DOUT
Device 1
START
(1)
CLK
CLK
INT
GPO0
GPO1
SCLK
MOSI
Host Processor
MISO
CLK
START
1
Device
1
CLK
DRDY
DRDY
1
START
CLK
START
2
Device
2
CLK
DRDY
DRDY
2
START
CLK
DRDY
1
DRDY
2
Note 1
Note 2
ADS1191
ADS1192
www.ti.com
SBAS566A – DECEMBER 2011 – REVISED SEPTEMBER 2012
When using multiple devices, the devices can be synchronized with the START signal. The delay from START to
the DRDY signal is fixed for a fixed data rate (see the START subsection of the SPI Interface section for more
details on the settling times). Figure 36 shows the behavior of two devices when synchronized with the START
signal.
(1) Start pulse must be at least one tMOD cycle wide.
(2) Settling time number uncertainty is one tMOD cycle.
Figure 36. Synchronizing Multiple Converters
Standard Mode
Figure 37 shows a configuration with two devices cascaded together. One of the devices is an ADS1192 (two-
channel) and the other is an ADS1192 (two-channel). Together, they create a system with four channels. DOUT,
SCLK, and DIN are shared. Each device has its own chip select. When a device is not selected by the
corresponding CS being driven to logic 1, the DOUT of this device is high-impedance. This structure allows the
other device to take control of the DOUT bus.
Figure 37. Multiple Device Configurations
Copyright © 2011–2012, Texas Instruments Incorporated
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Product Folder Links: ADS1191 ADS1192


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