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ICS8545BGLF Datasheet(PDF) 5 Page - Integrated Device Technology |
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ICS8545BGLF Datasheet(HTML) 5 Page - Integrated Device Technology |
5 / 15 page ICS8545 LOW SKEW, 1-TO-4, LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER IDT™ / ICS™ LVDS FANOUT BUFFER 5 ICS8545BG REV. D OCTOBER 28, 2008 Table 4C. LVDS DC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C AC Electrical Characteristics Table 5. AC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from VDD/2 of the input to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDD/2 of the input to the differential output crossing point. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. Symbol Parameter Test Conditions Minimum Typical Maximum Units VOD Differential Output Voltage 200 280 360 mV ∆V OD VOD Magnitude Change 40 mV VOS Offset Voltage 1.125 1.25 1.375 V ∆V OS VOS Magnitude Change 5 25 mV IOz High Impedance Leakage -10 ±1 +10 µA IOFF Power Off Leakage -20 ±1 +20 µA IOSD Differential Output Short Circuit Current -3.5 -5 mA IOS Output Short Circuit Current -3.5 -5 mA VOH Output Voltage High 1.34 1.6 V VOL Output Voltage Low 0.9 1.06 V Parameter Symbol Test Conditions Minimum Typical Maximum Units fMAX Output Frequency 650 MHz tPD Propagation Delay; NOTE 1 ƒ ≤ 650MHz 1.4 3.6 ns tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section 156.25MHz, Integration Range: 12kHz – 20MHz 0.13 ps tsk(o) Output Skew; NOTE 2, 4 40 ps tsk(pp) Part-to-Part Skew; NOTE 3, 4 500 ps tR / tF Output Rise/Fall Time 20% to 80% @ 50MHz 200 400 600 ps odc Output Duty Cycle 45 50 55 % |
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