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843003AGLFT Datasheet(PDF) 2 Page - Integrated Device Technology |
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843003AGLFT Datasheet(HTML) 2 Page - Integrated Device Technology |
2 / 21 page ICS843003 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER IDT™ / ICS™ LVPECL FREQUENCY SYNTHESIZER 2 ICS843003AG REV. A OCTOBER 23, 2008 Table 1. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Number Name Type Description 1 DIV_SELB0 Input Pulldown Division select pin for Bank B. Default = Low. LVCMOS/LVTTL interface levels. 2 VCO_SEL Input Pullup VCO select pin. When Low, the PLL is bypassed and the crystal reference or TEST_CLK (depending on XTAL_SEL setting) are passed directly to the output dividers. Has an internal pullup resistor so the PLL is not bypassed by default. LVCMOS/LVTTL interface levels. 3 MR Input Pulldown Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inverted outputs nQx to go high. When logic LOW, the internal dividers and the outputs are enabled. Has an internal pulldown resistor so the power-up default state of outputs and dividers are enabled. LVCMOS/LVTTL interface levels. 4VCCO_A Power Output supply pin for Bank A outputs. 5, 6 QA0, nQA0 Output Differential output pair. LVPECL interface levels. 7 OEB Input Pullup Output enable Bank B. Active High output enable. When logic HIGH, the output pair on Bank B is enabled. When logic LOW, the output pair drives differential Low (QB0 = Low, nQB0 = High). Has an internal pullup resistor so the default power-up state of outputs are enabled. LVCMOS/LVTTL interface levels. 8 OEA Input Pullup Output enable Bank A. Active High output enable. When logic HIGH, the 2 output pairs on Bank A are enabled. When logic LOW, the output pair drives differential Low (QA0 = Low, nQA0 = High). Has an internal pullup resistor so the default power-up state of outputs are enabled. LVCMOS/LVTTL interface levels. 9 FB_DIV Input Pulldown Feedback divide select. When Low (default), the feedback divider is set for ÷20. When HIGH, the feedback divider is set for ÷24. LVCMOS/LVTTL interface levels. 10 VCCA Power Analog supply pin. 11 VCC Power Core supply pin. 12 DIV_SELA0 Input Pullup Division select pin for Bank A. Default = HIGH. LVCMOS/LVTTL interface levels. 13 DIV_SELA1 Input Pulldown Division select pin for Bank A. Default = Low. LVCMOS/LVTTL interface levels. 14 VEE Power Negative supply pin. 15, 16 XTAL_OUT, XTAL_IN Input Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the input. XTAL_IN is also the overdrive pin if you want to overdrive the crystal circuit with a single-ended reference clock. 17 TEST_CLK Input Pulldown Single-ended reference clock input. Has an internal pulldown resistor to pull to low state by default. Can leave floating if using the crystal interface. LVCMOS/LVTTL interface levels. 18 XTAL_SEL Input Pullup Crystal select pin. Selects between the single-ended TEST_CLK or crystal interface. Has an internal pullup resistor so the crystal interface is selected by default. LVCMOS/LVTTL interface levels. 19, 20 nQB1, QB1 Output Differential output pair. LVPECL interface levels. 21, 22 nQB01, QB0 Output Differential output pair. LVPECL interface levels. 23 VCCO_B Power Output supply pin for Bank B outputs. 24 DIV_SELB1 Input Pullup Division select pin for Bank B. Default = High. LVCMOS/LVTTL interface levels. |
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