N25Q032A13E1241F datasheet(34/153 Pages) MICRON

Part #	N25Q032A13E1241F

Description	32-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase, XiP enabled, serial flash memory with 108 MHz SPI bus interface

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Manufacturer	MICRON [Micron Technology]

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Volatile and Non Volatile Registers

N25Q032 - 3 V

34/153

Micron Technology, Inc., reserves the right to change products or specifications without notice.

The Top/Bottom (TB) bit is used in conjunction with the Block Protect (BP2, BP1, BP0) bits

to determine if the protected area defined by the Block Protect bits starts from the top or the

bottom of the memory array:

When TB is reset to '0' (default value), the area protected by the Block Protect bits

starts from the top of the memory array.

When TB is set to '1', the area protected by the Block Protect bits starts from the bottom

of the memory array.

The TB bit cannot be written when the SRWD bit is set to '1' and the W pin is driven Low.

6.1.5

SRWD bit

The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write

Protect (W/VPP) signal. The Status Register Write Disable (SRWD) bit and the Write Protect

(W/VPP) signal allow the device to be put in the hardware protected mode (when the Status

Register Write Disable (SRWD) bit is set to '1', and Write Protect ((W/VPP) is driven Low). In

this mode, the non-volatile bits of the Status Register (TB, BP2, BP1, BP0) become read-

only bits and the Write Status Register (WRSR) instruction is no longer accepted for

execution.

6.2

Non Volatile Configuration Register

The Non Volatile Configuration Register (NVCR) bits affects the default memory

configuration after power-on. It can be used to make the memory start in the configuration to

fit the application requirements.

The device is delivered with Non Volatile Configuration Register (NVCR) bits all erased to 1

(FFFFh).

The purpose of the NVCR is to define the default memory settings after the power-on

sequence related to many features:

The number of dummy clock cycle for fast read instructions,

XIP mode configurations,

output driver strengths,

Reset (or Hold) disabling

Multiple I/O protocol enabling.

The NVCR can be read by the Read Non Volatile Configuration Register (RDNVCR)

instruction and written by the Write Non Volatile Configuration Register (WRNVCR) in all the

3 available SPI protocols. See the sections that follow as well as Table 3.: Non-Volatile

Configuration Register.

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N25Q032A13E1241F Datasheet(PDF) 34 Page - Micron Technology

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