PCM1723

3

SBAS057A

www.ti.com

ELECTRICAL CHARACTERISTICS

All specifications at +25

°C, +V

PCM1723

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

RESOLUTION

16

Bits

DATA FORMAT

Audio Data Interface Format

Data Bit Length

16/20/24 Selectable

Audio Data Format

MSB First, Binary Two’s Complement

32

44.1

48

kHz

16

22.05

24

kHz

64

88.2

96

kHz

PLL PERFORMANCE

26.73

27

27.27

MHz

Master Clock Output Frequency

4.096

36.864

MHz

Generated SYSCLK Frequency

Output Logic Level

VDC

(MCKO, SCKO)

0.5

VDC

Generated SYSCLK Jitter

Standard Dev

±150

ps

20

ms

Power-Up Time

To Programmed Frequency

15

30

ms

Generated SYSCLK Duty Cycle

40

50

60

%

DIGITAL INPUT LOGIC LEVEL

TTL

fs = 44.1kHz

–89

–80

dB

fs = 96kHz

–87

dB

THD+N at –60dB

fs = 44.1kHz

–31

dB

fs = 96kHz

–29

dB

Dynamic Range (EIAJ Method)

fs = 44.1kHz

90

94

dB

fs = 96kHz

91

dB

fs = 44.1kHz

90

96

dB

fs = 96kHz

95

dB

Channel Separation

fs = 44.1kHz

88

93

dB

DC ACCURACY

Gain Error

±1.0

±3.0

% of FSR

Gain Mismatch, Channel-to-Channel

±1.0

±2.0

% of FSR

Bipolar Zero Error

±30

mV

ANALOG OUTPUT

Output Voltage

Full Scale (–0dB)

Center Voltage

Load Impedance

AC Load

5

k

Ω

DIGITAL FILTER PERFORMANCE

Passband

0.445

Stop Band

0.555

Passband Ripple

±0.17

dB

Stop Band Attenuation

–35

dB

Delay Time

sec

De-emphasis Error

–0.2

+0.55

dB

INTERNAL ANALOG FILTER

–3dB Bandwidth

100

kHz

Passband Response

f = 20kHz

–0.16

dB

POWER SUPPLY REQUIREMENTS

Voltage Range

4.5

5

5.5

VDC

20

24

mA

TEMPERATURE RANGE

Operating

–25

+85

°C

Storage

–55

+100

°C

NOTES: (1) Sysclk transient is the maximum frequency lock time when the PLL frequency is changed.

(2) Dynamic performance specs are tested with 20kHz low pass filter and THD+N specs are tested with 30kHz LPF, 400Hz HPF, Average-Mode.

(3) SNR is tested at Infinite Zero Detection off.

(4) PLL evaluations tested with 1ns maximum jitter on the 27MHz input clock.