MCF5206FT33A datasheet(18/449 Pages) FREESCALE

Part #	MCF5206FT33A

Description	ColdFire Processor Core, DRAM Controller, Dual Universal Synchronous/Asynchronous Receiver/Transmitter (DUART)

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Manufacturer	FREESCALE [Freescale Semiconductor, Inc]

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18 / 449 page

TABLE OF CONTENTS (Continued)

Paragraph

Page

Number

Title

Number

MOTOROLA

USERÕS MANUAL

xiii

15.3.4

JTAG Bypass Register ...........................................................15-10

15.4

TAP Controller ..................................................................................15-10

15.5

Restrictions .......................................................................................15-12

15.6

Disabling the IEEE 1149.1 Standard Operation ...............................15-12

15.7

Motorola MCF5206 BSDL Description .............................................15-13

15.8

Obtaining the IEEE 1149.1 Standard ...............................................15-13

Section 16

Electrical Characteristics

16.1

Maximum Ratings ...............................................................................16-1

16.1.1

Supply, Input Voltage and Storage Temperature .....................16-1

16.1.2

Operating Temperature ............................................................16-1

16.1.3

Thermal Resistance .................................................................16-2

16.1.4

Output Loading .........................................................................16-2

16.2

DC Electrical Specifications ...............................................................16-2

16.3

AC Electrical Specifications ................................................................16-3

16.3.1

Clock Input Timing Specifications ............................................16-3

16.3.2

Clock Input Timing Diagram .....................................................16-3

16.3.3

Processor Bus Input Timing Specifications ..............................16-4

16.3.4

Input Timing Waveform Diagram ..............................................16-4

16.3.5

Processor Bus Output Timing Specifications ...........................16-5

16.3.6

Output Timing Waveform Diagram ...........................................16-6

16.3.7

Processor Bus Timing Diagrams ..............................................16-7

16.3.8

Timer Module AC Timing Specifications ................................16-13

16.3.9

Timer Module Timing Diagram ...............................................16-13

16.3.10

UART Module AC Timing Specifications ................................16-14

16.3.11

UART Module Timing Diagram ..............................................16-14

16.3.12

M-Bus Module AC Timing Specifications ...............................16-15

16.3.12.1

Input Timing Specifications Between SCL and SDA ...16-15

16.3.12.2

Output Timing Specifications Between SCL and SDA 16-15

16.3.12.3

Timing Specifications Between CLK and SCL, SDA ...16-16

16.3.13

M-Bus Module Timing Diagram ..............................................16-16

16.3.14

General Purpose I/O Port AC Timing Specifications ..............16-17

16.3.15

General Purpose I/O Port Timing Diagram ............................16-17

16.3.16

IEEE 1149.1 (JTAG) AC Timing Specifications ......................16-18

16.3.17

IEEE 1149.1 (JTAG) Timing Diagram ....................................16-18

Section 17

Mechanical Data

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