MCF5206FT33A datasheet(9/449 Pages) FREESCALE

Part #	MCF5206FT33A

Description	ColdFire Processor Core, DRAM Controller, Dual Universal Synchronous/Asynchronous Receiver/Transmitter (DUART)

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Manufacturer	FREESCALE [Freescale Semiconductor, Inc]

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TABLE OF CONTENTS (Continued)

Paragraph

Page

Number

Title

Number

iv

USERÕS MANUAL

MOTOROLA

3.5.10

Fault-on-Fault Halt ................................................................... 3-11

3.5.11

Reset Exception ....................................................................... 3-11

3.6

Instruction Execution Timing .............................................................. 3-11

3.6.1

Timing Assumptions ................................................................. 3-12

3.6.2

MOVE Instruction Execution Times ......................................... 3-12

Section 4

Instruction Cache

4.1

Features Of Instruction Cache ............................................................. 4-1

4.2

Instruction Cache Physical Organization ............................................. 4-1

4.3

Instruction Cache Operation ................................................................ 4-2

4.3.1

Interaction With Other Modules .................................................. 4-3

4.3.2

Memory Reference Attributes .................................................... 4-3

4.3.3

Cache Coherency and Invalidation ............................................ 4-3

4.3.4

Reset .......................................................................................... 4-4

4.3.5

Cache Miss Fetch Algorithm/Line Fills ....................................... 4-4

4.4

Instruction Cache Programming Model ................................................ 4-5

4.4.1

Instruction Cache Registers Memory Map ................................. 4-5

4.4.2

Instruction Cache Register ......................................................... 4-6

4.4.2.1

Cache Control Register (CACR) ..................................... 4-6

4.4.2.2

Access Control Registers (ACR0, ACR1) ....................... 4-8

Section 5

SRAM

5.1

SRAM Features .................................................................................... 5-1

5.2

SRAM Operation .................................................................................. 5-1

5.3

Programming Model ............................................................................. 5-1

5.3.1

SRAM Register Memory Map .................................................... 5-1

5.3.2

SRAM Registers ......................................................................... 5-2

5.3.2.1

SRAM Base Address Register (RAMBAR) ..................... 5-2

5.3.3

SRAM Initialization ..................................................................... 5-3

5.3.4

Power Management ................................................................... 5-4

Section 6

Bus Operation

6.1

Features ............................................................................................... 6-1

6.2

Bus And Control Signals ...................................................................... 6-1

6.2.1

Address Bus (A[27:0]) ................................................................ 6-1

6.2.2

Data Bus (D[31:0]) ..................................................................... 6-2

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