CY7C25682KV18

CY7C25702KV18

Document Number: 001-66483 Rev. *B

Page 6 of 29

CQ

Echo Clock Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock

(K) of the DDR II+. The timing for the echo clocks is shown in the Switching Characteristics on page 23.

CQ

Echo Clock Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock

(K) of the DDR II+. The timing for the echo clocks is shown in the Switching Characteristics on page 23.

ZQ

Input

Output Impedance Matching Input. This input is used to tune the device outputs to the system data

enables the minimum impedance mode. This pin cannot be connected directly to GND or left

unconnected.

DOFF

Input

PLL Turn Off

 Active LOW. Connecting this pin to ground turns off the PLL inside the device. The

timing in the PLL turned off operation differs from those listed in this data sheet. For normal operation,

this pin can be connected to a pull up through a 10 K

 or less pull up resistor. The device behaves in

DDR I mode when the PLL is turned off. In this mode, the device can be operated at a frequency of up

to 167 MHz with DDR I timing.

TDO

Output

TDO Pin for JTAG.

TCK

Input

TCK Pin for JTAG.

TDI

Input

TDI Pin for JTAG.

TMS

Input

TMS Pin for JTAG.

NC

N/A

Not Connected to the Die. Can be tied to any voltage level.

NC/144M

Input

Not Connected to the Die. Can be tied to any voltage level.

NC/288M

Input

Not Connected to the Die. Can be tied to any voltage level.

Input-

Reference

Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and AC

measurement points.

Power Supply Power Supply Inputs to the Core of the Device.

Ground

Ground for the Device.

Power Supply Power Supply Inputs for the Outputs of the Device.

Pin Name

I/O

Pin Description