CY7C25702KV18-550BZXC datasheet(10/29 Pages) CYPRESS

Part #	CY7C25702KV18-550BZXC

Description	72-Mbit DDR II SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT

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Manufacturer	CYPRESS [Cypress Semiconductor]

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CY7C25682KV18

CY7C25702KV18

Document Number: 001-66483 Rev. *B

Page 10 of 29

Write Cycle Descriptions

The write cycle description table for CY7C25702KV18 follows. [11, 12]

BWS0 BWS1 BWS2 BWS3

K

Comments

LLLL

L–H

–

During the data portion of a write sequence, all four bytes (D[35:0]) are written into

the device.

LLLL

–

L–H During the data portion of a write sequence, all four bytes (D[35:0]) are written into

the device.

L

H

L–H

–

During the data portion of a write sequence, only the lower byte (D[8:0]) is written

into the device. D[35:9] remains unaltered.

L

H

–

L–H During the data portion of a write sequence, only the lower byte (D[8:0]) is written

into the device. D[35:9] remains unaltered.

H

L

H

L–H

–

During the data portion of a write sequence, only the byte (D[17:9]) is written into

the device. D[8:0] and D[35:18] remains unaltered.

H

L

H

–

L–H During the data portion of a write sequence, only the byte (D[17:9]) is written into

the device. D[8:0] and D[35:18] remains unaltered.

H

L

H

L–H

–

During the data portion of a write sequence, only the byte (D[26:18]) is written into

the device. D[17:0] and D[35:27] remains unaltered.

H

L

H

–

L–H During the data portion of a write sequence, only the byte (D[26:18]) is written into

the device. D[17:0] and D[35:27] remains unaltered.

H

L

L–H

–

During the data portion of a write sequence, only the byte (D[35:27]) is written into

the device. D[26:0] remains unaltered.

H

L

–

L–H During the data portion of a write sequence, only the byte (D[35:27]) is written into

the device. D[26:0] remains unaltered.

HHHH

L–H

–

No data is written into the device during this portion of a write operation.

HHHH

–

L–H No data is written into the device during this portion of a write operation.

Notes

11. X = “Don’t Care,” H = Logic HIGH, L = Logic LOW,



represents rising edge.

12. Is based on a write cycle that was initiated in accordance with Write Cycle Descriptions. BWS0, BWS1, BWS2, and BWS3 can be altered on different portions of a write

cycle, as long as the setup and hold requirements are achieved.

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CY7C25702KV18-550BZXC Datasheet(PDF) 10 Page - Cypress Semiconductor

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