CY7C1370D, CY7C1372D

Document Number: 38-05555 Rev. *N

Page 9 of 31

Truth Table

The Truth Table for CY7C1370D and CY7C1372D follows. [1, 2, 3, 4, 5, 6, 7]

Operation

Address Used CE

ZZ

DQ

Deselect cycle

None

H

L

L

X

X

X

L

L–H

Tri-state

Continue deselect cycle

None

X

L

H

X

X

X

L

L–H

Tri-state

Read cycle (begin burst)

External

L

L

L

H

X

L

L

L–H Data out (Q)

Read cycle (continue burst)

Next

X

L

H

X

X

L

L

L–H Data out (Q)

NOP/dummy read (begin burst)

External

L

L

L

H

X

H

L

L–H

Tri-state

Dummy read (continue burst)

Next

X

L

H

X

X

H

L

L–H

Tri-state

Write cycle (begin burst)

External

L

L

L

L

L

X

L

L–H

Data in (D)

Write cycle (continue burst)

Next

X

L

H

X

L

X

L

L–H

Data in (D)

NOP/write abort (begin burst)

None

L

L

L

L

H

X

L

L–H

Tri-state

Write abort (continue burst)

Next

X

L

H

X

H

X

L

L–H

Tri-state

Ignore clock edge (stall)

Current

X

L

X

X

X

X

H

L–H

–

Sleep mode

None

X

H

X

X

X

X

X

X

Tri-state

Notes

1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = L signifies at least one Byte Write Select is active, BWx = Valid

signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.

3. When a write cycle is detected, all I/Os are tristated, even during byte writes.

4. The DQ and DQP pins are controlled by the current cycle and the OE signal.

5. CEN = H inserts wait states.

6. Device will power-up deselected and the I/Os in a tristate condition, regardless of OE.