SN74VMEH22501AEP

8BIT UNIVERSAL BUS TRANSCEIVER AND TWO 1BIT BUS TRANSCEIVERS

WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND 3STATE OUTPUTS

SCES625 − FEBRUARY 2005

9

POST OFFICE BOX 655303

timing requirements over recommended operating conditions for UBT transceiver (unless otherwise

noted) (see Figures 1 and 2)

MIN

MAX

UNIT

fclock

Clock frequency

120

MHz

tw

Pulse duration

LE high

2.5

ns

tw

Pulse duration

CLK high or low

3

ns

3A before CLK

↑

Data high

2.1

3A before CLK

↑

Data low

2.2

3A before LE

↓

CLK high

2

tsu

Setup time

3A before LE

↓

CLK low

2

ns

tsu

Setup time

3B before CLK

↑

Data high

2.5

ns

3B before CLK

↑

Data low

2.7

3B before LE

↓

CLK high

2

3B before LE

↓

CLK low

2

3A after CLK

↑

Data high

0

3A after CLK

↑

Data low

0

3A after LE

↓

CLK high

1

th

Hold time

3A after LE

↓

CLK low

1

ns

th

Hold time

3B after CLK

↑

Data high

0

ns

3B after CLK

↑

Data low

0

3B after LE

↓

CLK high

1

3B after LE

↓

CLK low

1

switching characteristics over recommended operating conditions for bus transceiver function

(unless otherwise noted) (see Figures 1 and 2)

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

MIN

TYP

MAX

UNIT

tPLH

1A or 2A

1B or 2B

4.5

9.2

ns

tPHL

1A or 2A

1B or 2B

4.2

7.8

ns

tPLH

1A or 2A

1Y or 2Y

6.2

14.5

ns

tPHL

1A or 2A

1Y or 2Y

6.1

13

ns

tPZH

OEAB

1B or 2B

3.6

8.1

ns

tPZL

OEAB

1B or 2B

3.4

7.8

ns

tPHZ

OEAB

1B or 2B

3.3

9.7

ns

tPLZ

OEAB

1B or 2B

1.8

4.8

ns

tr

Transition time, B port (10%−90%)

4.3

ns

tf

Transition time, B port (90%−10%)

4.3

ns

tPLH

1B of 2B

1Y or 2Y

1.6

5.6

ns

tPHL

1B of 2B

1Y or 2Y

1.6

5.6

ns

tPZH

OEBY

1Y or 2Y

1.2

5.6

ns

tPZL

OEBY

1Y or 2Y

1.8

4.9

ns

tPHZ

OEBY

1Y or 2Y

0.9

5.4

ns

tPLZ

OEBY

1Y or 2Y

1.4

4.5

ns