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TMS320LBC57PGE80 Datasheet(PDF) 55 Page - Texas Instruments |
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TMS320LBC57PGE80 Datasheet(HTML) 55 Page - Texas Instruments |
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55 / 94 page  TMS320C5x, TMS320LC5x DIGITAL SIGNAL PROCESSORS SPRS030A – APRIL 1995 – REVISED APRIL 1996 55 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 PLL clock generator option An external frequency source can be used by injecting the frequency directly into CLKIN2‡ with X1 left unconnected and X2 connected to VDD. This external frequency is multiplied by the factors shown in Table 9 and Table 10 to generate the internal machine cycle. The multiply-by-one option is available on the ’C50, ’LC50, ’C51, ’LC51, ’C53, ’LC53, ’C53S and ’LC53S. The multiply-by-two option is available on the ’C52 and ’LC52. Multiplication factors of 1, 2, 3, 4, 5, and 9 are available on the ’LC56, ’LC57, ’C57S and ’LC57S. Refer to Table 9 and Table 10 for appropriate configuration of the CLKMD1, CLKMD2 and CLKMD3 pins to generate the desired PLL multiplication factor. The external frequency injected must conform to the specifications listed in the timing requirements table. switching characteristics over recommended operating conditions [H = 0.5 tc(CO)] (’320C5x only) (see Figure 14) PARAMETER ’320C5x-40 ’320C5x-57 UNIT PARAMETER MIN TYP MAX MIN TYP MAX UNIT tc(CO) Cycle time, CLKOUT1 48.8 75 35 75 ns tf(CO) Fall time, CLKOUT1 5 5 ns tr(CO) Rise time, CLKOUT1 5 5 ns tw(COL) Pulse duration, CLKOUT1 low H – 3† H H + 2† H – 3† H H + 2† ns tw(COH) Pulse duration, CLKOUT1 high H – 3† H H + 2† H – 3† H H + 2† ns td(C2H-COH) Delay time, CLKIN2 high to CLKOUT1 high 2 9 16 2 9 16 ns td(TP) Delay time, transitory phase—PLL synchronized after CLKIN2 supplied† 1000tc(C2) 1000tc(C2) ns PARAMETER ’320C5x-80 ’320C5x-100 UNIT PARAMETER MIN TYP MAX MIN TYP MAX UNIT tc(CO) Cycle time, CLKOUT1 25 55 20 45 ns tf(CO) Fall time, CLKOUT1 4 4 ns tr(CO) Rise time, CLKOUT1 4 4 ns tw(COL) Pulse duration, CLKOUT1 low H – 3† H H + 2† H – 3† H H + 2† ns tw(COH) Pulse duration, CLKOUT1 high H – 3† H H + 2† H – 3† H H + 2† ns td(C2H-COH) Delay time, CLKIN2 high to CLKOUT1 high 1 8 15 1 8 15 ns td(TP) Delay time, transitory phase—PLL synchronized after CLKIN2 supplied† 1000tc(C2) 1000tc(C2) ns † Values assured by design and not tested ‡ On the TMS320C57S devices, CLKIN2 functions as the PLL clock input. |
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