IDT2309-1HPGGI datasheet(2/10 Pages) IDT

Part #	IDT2309-1HPGGI

Description	3.3V ZERO DELAY CLOCK BUFFER Phase-Lock Loop Clock Distribution

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Manufacturer	IDT [Integrated Device Technology]

Direct Link	http://www.idt.com

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COMMERCIALANDINDUSTRIALTEMPERATURERANGES

IDT2309

3.3VZERODELAYCLOCKBUFFER

PINCONFIGURATION

SOIC/ TSSOP

TOP VIEW

Symbol

Rating

Max.

Unit

VDD

SupplyVoltageRange

–0.5 to +4.6

V

VI(2)

InputVoltageRange(REF)

–0.5 to +5.5

V

VI

InputVoltageRange

–0.5to

V

(except REF)

VDD+0.5

IIK (VI < 0)

InputClampCurrent

–50

mA

IO (VO = 0 to VDD)

ContinuousOutputCurrent

±50

mA

VDD or GND

ContinuousCurrent

±100

mA

TA = 55°C

Maximum Power Dissipation

0.7

W

(instillair)(3)

TSTG

StorageTemperatureRange

–65to+150

°C

Operating

CommercialTemperature

0 to +70

°C

Temperature

Range

Operating

IndustrialTemperature

-40 to +85

°C

Temperature

Range

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

2. The input and output negative-voltage ratings may be exceeded if the input and output

clamp-current ratings are observed.

3. The maximum package power dissipation is calculated using a junction temperature

of 150°C and a board trace length of 750 mils.

NOTES:

1. Weak pull down on all outputs.

2. Weak pull ups on these inputs.

PINDESCRIPTION

ABSOLUTEMAXIMUMRATINGS(1)

Pin Name

Pin Number

Type

Functional Description

REF

1

IN

Input reference clock, 5 Volt tolerant input

CLKA1(1)

2

Out

Output clock for bank A

CLKA2(1)

3

Out

Output clock for bank A

VDD

4, 13

PWR

3.3V Supply

GND

5, 12

GND

Ground

CLKB1(1)

6

Out

Output clock for bank B

CLKB2(1)

7

Out

Output clock for bank B

S2(2)

8

IN

Select input Bit 2

S1(2)

9

IN

Select input Bit 1

CLKB3(1)

10

Out

Output clock for bank B

CLKB4(1)

11

Out

Output clock for bank B

CLKA3(1)

14

Out

Output clock for bank A

CLKA4(1)

15

Out

Output clock for bank A

CLKOUT(1)

16

Out

Output clock, internal feedback on this pin

APPLICATIONS:

•

SDRAM

•

Telecom

•

Datacom

•

PC Motherboards/Workstations

•

Critical Path Delay Designs

REF

CLKA1

S2

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

1

CLKA2

GND

CLKB1

CLKOUT

CLKA4

GND

S1

VDD

CLKB2

CLKB3

CLKB4

CLKA3

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