 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
IDT5V9950PFGI Datasheet(PDF) 6 Page - Integrated Device Technology |
|
||||||||||||||||||||||||||||||
IDT5V9950PFGI Datasheet(HTML) 6 Page - Integrated Device Technology |
|
|
6 / 9 page  6 INDUSTRIALTEMPERATURERANGE IDT5V9950 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II JR. SWITCHING CHARACTERISTICS OVER OPERATING RANGE Symbol Parameter Min. Typ. Max. Unit FNOM VCO Frequency Range See Programmable Skew Range and Resolution Table tRPWH REF Pulse Width HIGH(1) 2— — ns tRPWL REF Pulse Width LOW(1) 2— — ns tU Programmable Skew Time Unit See Control Summary Table tSKEWPR Zero Output Matched-Pair Skew (xQ0, xQ1)(2,3) — 50 185 ps tSKEW0 Zero Output Skew (All Outputs)(4) — 0.1 0.25 ns tSKEW1 Output Skew (Rise-Rise, Fall-Fall, Same Class Outputs)(5) — 0.1 0.25 ns tSKEW2 Output Skew (Rise-Fall, Nominal-Inverted, Divided-Divided)(5) — 0.2 0.5 ns tSKEW3 Output Skew (Rise-Rise, Fall-Fall, Different Class Outputs)(5) — 0.15 0.5 ns tSKEW4 Output Skew (Rise-Fall, Nominal-Divided, Divided-Inverted)(2) — 0.3 0.9 ns tDEV Device-to-Device Skew(2,6) — — 0.75 ns t( φ) REF Input to FB Static Phase Offset)(7) −0.25 — 0.25 ns tODCV Output Duty Cycle Variation from 50% −10 1 ns tPWH Output HIGH Time Deviation from 50%(8) — — 1.5 ns tPWL Output LOW Time Deviation from 50%(9) —— 2 ns tORISE Output Rise Time 0.15 0.7 1.5 ns tOFALL OutputFallTime 0.15 0.7 1.5 ns tLOCK PLL Lock Time(10) — — 0.5 ms tCCJH Cycle-to-Cycle Output Jitter (peak-to-peak) — — 100 (divide by 1 output frequency, FS = H, FB divide-by-n=1,2) tCCJM Cycle-to-Cycle Output Jitter (peak-to-peak) — — 150 ps (divide by 1 output frequency, FS = M) tCCJL Cycle-to-Cycle Output Jitter (peak-to-peak) — — 200 (divide by 1 output frequency, FS = L, FREF > 3MHz) NOTES: 1. Refer to Input Timing Requirements table for more detail. 2. Skew is the time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with the specified load. 3. tSKEWPR is the skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0tU. 4. tSK(0) is the skew between outputs when they are selected for 0tU. 5. There are 3 classes of outputs: Nominal (multiple of tU delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and Divided (3Qx and 4Qx only in Divide-by-2 or Divide- by-4 mode). Test condition: nF0:1=MM is set on unused outputs. 6. tDEV is the output-to-output skew between any two devices operating under the same conditions (VDDQ, VDD, ambient temperature, air flow, etc.) 7. t φ is measured with REF input rise and fall times (from 0.8V to 2V) of 0.5ns. Measured from 1.5V on REF to 1.5V on FB. 8. Measured at 2V. 9. Measured at 0.8V. 10. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VDD/VDDQ is stable and within normal operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits. |
Similar Part No. - IDT5V9950PFGI |
|
Similar Description - IDT5V9950PFGI |
|
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
