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5962-8855206XA Datasheet(PDF) 7 Page - Integrated Device Technology |
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5962-8855206XA Datasheet(HTML) 7 Page - Integrated Device Technology |
7 / 10 page 6.42 IDT71256S/L CMOS Static RAM 256K (32K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges 7 Timing Waveform of Read Cycle No. 2(1,2,4) NOTES: 1. WE is HIGH for Read Cycle. 2. Device is continuously selected, CS is LOW. 3. Address valid prior to or coincident with CS transition LOW. 4. OE is LOW. 5. Transition is measured ±200mV from steady state. Timing Waveform of Read Cycle No. 1(1) ADDRESS CS OE DATAOUT tRC tAA tOH tOE tACS tCLZ (5) tOLZ (5) 2946 drw 07 tCHZ(5) tOHZ(5) 2946 drw 08 ADDRESS DATAOUT tRC tAA tOH tOH , Timing Waveform of Read Cycle No. 2(1,3,4) CS DATAOUT tACS tCLZ (5) 2946 drw 09 tCHZ(5) |
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