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DAC8043UCG4 Datasheet(PDF) 7 Page - Texas Instruments |
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DAC8043UCG4 Datasheet(HTML) 7 Page - Texas Instruments |
7 / 11 page 7 ® DAC8043 AMPLIFIER OFFSET VOLTAGE The output amplifier used with the DAC8043 should have low input offset voltage to preserve the transfer function linearity. The voltage output of the amplifier has an error component which is the offset voltage of the op amp multi- plied by the “noise gain” of the circuit. This “noise gain” is equal to (RF/RO + 1) where RO is the output impedance of the D/A IOUT terminal and RF is the feedback network imped- ance. The nonlinearity occurs due to the output impedance varying with code. If the 0 code case is excluded (where RO = infinity), the RO will vary from R to 3R providing a “noise gain” variation between 4/3 and 2. In addition, the variation of RO is nonlinear with code, and the largest steps in RO occur at major code transitions where the worst differential nonlinearity is also likely to be experienced. The nonlinearity seen at the amplifier output is 2V OS – 4VOS /3 = 2VOS/3. Thus, to maintain good nonlinearity the op amp offset should be much less than 1/2LSB. UNIPOLAR CONFIGURATION Figure 3 shows DAC8043 in a typical unipolar (two-quad- rant) multiplying configuration. The analog output values versus digital input code are listed in Table I. The operational amplifiers used in this circuit can be single amplifiers such as the OPA602, or a dual amplifier such as the OPA2107. C1 provides phase compensation to minimize settling time and overshoot when using a high speed operational amplifier. If an application requires the D/A to have zero gain error, the circuit shown in Figure 4 may be used. Resistor R2 induces a positive gain error greater than worst-case initial negative gain error. Trim resistor R1 provides a variable negative gain error and have sufficient trim range to correct for the worst- case initial positive gain error plus the error produced by R2. BIPOLAR CONFIGURATION Figure 5 shows the DAC8043 in a typical bipolar (four- quadrant) multiplying configuration. The analog output val- ues versus digital input code are listed in Table II. The operational amplifiers used in this circuit can be single amplifiers such as the OPA602 or a dual amplifier such as the OPA2107. C1 provides phase compensation to minimize settling time and overshoot when using a high speed opera- tional amplifier. The bipolar offset resistors R1–R2 should be ratio-matched to 0.01% to ensure the specified gain error performance. DATA INPUT ANALOG OUTPUT MSB ↓↓ LSB 1111 1111 1111 –VREF (4095/4096) 1000 0000 0000 –VREF (2048/4096) = –1/2VREF 0000 0000 0001 –VREF (1/4096) 0000 0000 0000 0 Volts TABLE I. Unipolar Output Code. DATA INPUT ANALOG OUTPUT MSB ↓↓ LSB 1111 1111 1111 +V REF (2047/2048) 1000 0000 0001 +V REF (1/2048) 1000 0000 0000 0 Volts 0111 1111 1111 –V REF (1/2048) 0000 0000 0000 –V REF (2048/2048) TABLE II. Bipolar Output Code. R 2 Ω 47 DAC I OUT GND R FB C 1 10pF V OUT – + A1 V DD +5V C D A1 OPA602 or 1/2 OPA2107. + 1µF V IN R 100 1 Ω REF V DAC8043 FIGURE 4. Unipolar Configuration with Gain Trim. FIGURE 3. Unipolar Configuration. DAC I OUT GND R FB C 1 10pF DAC8043 V OUT – + A1 V REF V DD +5V C D A1 OPA602 or 1/2 OPA2107. + 1µF FIGURE 5. Bipolar Configuration. R 3 10k 1 C 10pF DAC V REF V DD +5V C D R 2 Ω 20k V OUT A1 A1–A2, OPA602 or 1/2 OPA2107. A2 – + Ω R 1 Ω 20k I OUT R FB – + GND 1µF + DAC8043 |
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