11

®

ADS7818

Table II offers a look at the two different modes of operation

and the difference in power consumption.

the conversion will terminate immediately, before all 12-bits

have been decided. This can be a very useful feature when

a resolution of 12-bits is not needed. An example would be

when the converter is being used to monitor an input voltage

until some condition is met. At that time, the full resolution

of the converter would then be used. Short-cycling the

conversion can result in a faster conversion rate or lower

power dissipation.

There are several very important items shown in Figure 6.

The conversion currently in progress is terminated when

CONV is taken HIGH during the conversion and then taken

Note that if CONV goes LOW during the 13th clock cycle,

then the LSB first mode will be entered (Figure 5). Also,

when CONV goes LOW, the DATA output immediately

transitions to high impedance. If the output bit that is present

during that clock period is needed, CONV must not go LOW

until the bit has been properly latched into the receiving

logic.

DATA FORMAT

The ADS7818 output data is in straight binary format as

shown in Figure 7. This figure shows the ideal output code

for the given input voltage and does not include the effects

of offset, gain, or noise.

POWER WITH

POWER WITH

CLK = 8MHz

500kHz

11mW

11mW

250kHz

10mW

7mW

100kHz

9mW

4mW

TABLE II. Power Consumption versus CLK Input.

LSB FIRST DATA TIMING

Figure 5 shows a method to transmit the digital result in a

least-significant bit (LSB) format. This mode is entered

when CONV is pulled HIGH during the conversion (before

the end of the 12th clock) and then pulled LOW during the

13th clock (when D0, the LSB, is being transmitted). The

next 11 clocks then repeat the serial data, but in an LSB first

format. The converter enters the power-down mode during

the 13th clock and resumes normal operation when CONV

goes HIGH.

SHORT-CYCLE TIMING

The conversion currently in progress can be “short-cycled”

with the technique shown in Figure 6. This term means that

FIGURE 6. Short-cycle Timing.

D11

(MSB)

DATA

CONVERSION IN PROGRESS

IDLE

IDLE

CLK

CONV

POWER MODE

FULL POWER

LOW POWER

D10

D8

D9

D7

12

3

5

46

7

D6

INTERNAL

CONVERSION

STATE

t

CVDD

t

CVL

t

CVH

HOLD

SAMPLE

SAMPLE/HOLD

MODE

NOTE: (1) The conversion currently in progress can be stopped by pulling CONV LOW during the conversion. This must occur at

least t

mode when CONV is pulled LOW.

(1)

t

CVPD