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DS125DF410 Datasheet(PDF) 6 Page - Texas Instruments |
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DS125DF410 Datasheet(HTML) 6 Page - Texas Instruments |
6 / 44 page DS125DF410 SNLS398E – JANUARY 2012 – REVISED MAY 2013 www.ti.com ELECTRICAL CHARACTERISTICS Over recommended operating supply and temperature ranges with default register settings unless otherwise specified. (1) Symbol Parameter Conditions Min Typ Max Units POWER PD Power Supply Consumption Average Power Consumption (DFE 720 mW Powered-Up and Enabled)(2) Max Transient Power Supply 500 610 mA Current(3) NTPS Supply Noise Tolerance(4) 50 Hz to 100 Hz 100 mVP-P 100 Hz to 10 MHz 40 mVP-P 10 MHz to 5.0 GHz 10 mVP-P 2.5V LVCMOS DC SPECIFICATIONS VIH High Level Input Voltage 1.75 VDD V VIL Low Level Input Voltage GND 0.7 V VOH High Level Output Voltage IOH = -3mA 2.0 V VOL Low Level Output Voltage IOL = 3mA 0.4 V IIN Input Leakage Current VIN = VDD +10 μA VIN = GND -10 μA IIH Input High Current (EN_SMB pin) VIN = VDD +55 μA IIL Input Low Current (EN_SMB pin) VIN = GND -110 μA 3.3 V LVCMOS DC SPECIFICATIONS (SDA, SDC, INT) VIH High Level Input Voltage VDD = 2.5 V 1.75 3.6 V VIL Low Level Input Voltage VDD = 2.5 V GND 0.7 V VOL Low Level Output Voltage IPULLUP = 3mA 0.4 V IIH Input High Current VIN = 3.6 V, VDD = 2.5V +20 +40 μA IIL Input Low Current VIN = GND, VDD = 2.5V -10 +10 μA fSDC SMBus clock rate 100 400 KHz DATA BIT RATES RB Bit Rate Range 9.8 12.5 Gbps SIGNAL DETECT SDH Signal Detect ON Threshold Level Default input signal level to assert 70 mVp-p signal detect, 10.3125 Gbps, PRBS- 31 SDL Signal Detect OFF Threshold Level Default input signal level to de-assert 10 mVp-p signal detect, 10.3125 Gbps, PRBS- 31 (1) Typical values represent most likely parametric norms at VDD = 2.5V, TA = 25°C., and at the Recommended Operation Conditions at the time of product characterization. (2) VDD= 2.5V, TA = 25°C. All four channels active and locked. DFE is powered-up and enabled. (3) Max momentary power supply current lasting less than 1s. The retimer may consume more power than the maximum average power rating during the time required to acquire CDR lock. (4) Allowed supply noise (mVP-P sine wave) under typical conditions. 6 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: DS125DF410 |
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