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DS110RT410 Datasheet(PDF) 4 Page - Texas Instruments |
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DS110RT410 Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 40 page  DS110RT410 SNLS460 – MAY 2013 www.ti.com Pin Functions Pin Descriptions Pin Name Pin # I/O, Type Description HIGH-SPEED DIFFERENTIAL I/O RXP0 1 I, CML Inverting and non-inverting CML-compatible differential inputs to the equalizer. RXN0 2 Nominal differential input impedance = 100 Ω. RXP1 4 I, CML Inverting and non-inverting CML-compatible differential inputs to the equalizer. RXN1 5 Nominal differential input impedance = 100 Ω. RXP2 8 I, CML Inverting and non-inverting CML-compatible differential inputs to the equalizer. RXN2 9 Nominal differential input impedance = 100 Ω. RXP3 11 I, CML Inverting and non-inverting CML-compatible differential inputs to the equalizer. RXN3 12 Nominal differential input impedance = 100 Ω. TXP0 36 O, CML Inverting and non-inverting CML-compatible differential outputs from the driver. TXN0 35 Nominal differential output impedance = 100 Ω. TXP1 33 O, CML Inverting and non-inverting CML-compatible differential outputs from the driver. TXN1 32 Nominal differential output impedance = 100 Ω. TXP2 29 O, CML Inverting and non-inverting CML-compatible differential outputs from the driver. TXN2 28 Nominal differential output impedance = 100 Ω. TXP3 26 O, CML Inverting and non-inverting CML-compatible differential outputs from the driver. TXN3 25 Nominal differential output impedance = 100 Ω. LOOP FILTER CONNECTION PINS LPF_CP_0 47 I/O, analog Loop filter connection LPF_REF_0 48 Place a 22 nF ± 10% Capacitor between LPF_CP_0 and LPF_REF_0 LPF_CP_1 38 I/O, analog Loop filter connection LPF_REF_1 37 Place a 22 nF ± 10% Capacitor between LPF_CP_1 and LPF_REF_1 LPF_CP_2 23 I/O, analog Loop filter connection LPF_REF_2 24 Place a 22 nF ± 10% Capacitor between LPF_CP_2 and LPF_REF_2 LPF_CP_3 14 I/O, analog Loop filter connection LPF_REF_3 13 Place a 22 nF ± 10% Capacitor between LPF_CP_3 and LPF_REF_3 REFERENCE CLOCK I/O REFCLK_IN 19 I, 2.5V analog Input is 2.5 V, 25 MHz ± 100 ppm reference clock from external oscillator No stringent phase noise requirement REFCLK_OUT 42 O, 2.5V analog Output is 2.5 V, buffered replica of reference clock input for connecting multiple DS110RT410s on a board LOCK INDICATOR PINS LOCK_0 45 O, 2.5V Output is 2.5 V, the pin is high when CDR lock is attained on the corresponding LOCK_1 40 LVCMOS channel. LOCK_2 21 Note that these pins are shared with SMBus address strap input functions read LOCK_3 16 at startup. SMBus MASTER MODE PINS ALL_DONE 41 O, 2.5V Output is 2.5 V, the pin goes low to indicate that the SMBus master EEPROM LVCMOS read has been completed. READ_EN 44 I, 2.5V Input is 2.5 V, a transition from high to low starts the load from the external LVCMOS EEPROM. The READ_EN pin must be tied low when in SMBus slave mode. INTERRUPT OUTPUT INT 43 O, 3.3V Open Used to signal horizontal or vertical eye opening out of tolerance, loss of signal Drain detect, or CDR unlock External 2K Ω to 5KΩ pull-up resistor is required. Pin is 3.3 V LVCMOS tolerant. SERIAL MANAGEMENT BUS (SMBus) INTERFACE EN_SMB 20 I, 2.5V analog Input is 2.5 V, selects SMBus master mode or SMBus slave mode. EN_SMB = High for slave mode EN_SMB = Float for master mode Tie READ_EN pin low for SMBus slave mode. See Table 3 SDA 18 I/O, 3.3V Data Input / Open Drain Output LVCMOS, Open External 2K Ω to 5KΩ pull-up resistor is required. Drain Pin is 3.3 V LVCMOS tolerant. 4 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DS110RT410 |
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