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CY7C263-25JC Datasheet(PDF) 1 Page - Cypress Semiconductor

Part # CY7C263-25JC
Description  8K x 8 Power-Switched and Reprogrammable PROM
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C263-25JC Datasheet(HTML) 1 Page - Cypress Semiconductor

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8K x 8 Power-Switched and Reprogrammable PROM
CY7C261
CY7C263/CY7C264
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-04010 Rev. **
Revised March 4, 2002
Features
• CMOS for optimum speed/power
• Windowed for reprogrammability
• High speed
— 20 ns (commercial)
— 25 ns (military)
• Low power
— 660 mW (commercial)
— 770 mW (military)
• Super low standby power (7C261)
— Less than 220 mW when deselected
— Fast access: 20 ns
• EPROM technology 100% programmable
• Slim 300-mil or standard 600-mil packaging available
• 5V
± 10% V
CC, commercial and military
• Capable of withstanding greater than 2001V static dis-
charge
• TTL-compatible I/O
• Direct replacement for bipolar PROMs
Functional Description
The CY7C261, CY7C263, and CY7C264 are high-perfor-
mance 8192-word by 8-bit CMOS PROMs. When deselected,
the 7C261 automatically powers down into a low-power stand-
by mode. It is packaged in a 300-mil-wide package. The 7C263
and 7C264 are packaged in 300-mil-wide and 600-mil-wide
packages respectively, and do not power down when deselect-
ed. The reprogrammable packages are equipped with an era-
sure window; when exposed to UV light, these PROMs are
erased and can then be reprogrammed. The memory cells uti-
lize proven EPROM floating-gate technology and byte-wide in-
telligent programming algorithms.
The CY7C261, CY7C263, and CY7C264 are plug-in replace-
ments for bipolar devices and offer the advantages of lower
power, superior performance and programming yield. The
EPROM cell requires only 12.5V for the supervoltage and low
current requirements allow for gang programming. The
EPROM cells allow for each memory location to be tested
100%, as each location is written into, erased, and repeatedly
exercised prior to encapsulation. Each PROM is also tested for
AC performance to guarantee that after customer program-
ming the product will meet DC and AC specification limits.
Read is accomplished by placing an active LOW signal on CS.
The contents of the memory location addressed by the ad-
dress line (A0−A12) will become available on the output lines
(O0−O7).
For an 8K x 8 Registered PROM, see theCY7C265.
Logic Block Diagram
Pin Configurations
O7
O6
O5
O4
O3
O2
O1
O0
ADDRESS
DECODER
PROGRAM–
MABLE
ARRAY
COLUMN
MULTI–
PLEXER
POWER DOWN
(7C261)
A0
A1
A2
A3
A4
A5
A6
A8
A9
A10
A11
A12
CS
GND
1
2
3
4
5
6
7
8
9
10
11
14
15
16
20
19
18
17
21
24
23
22
Top View
DIP/Flatpack
A6
A5
A4
A3
A2
A1
A0
O0
A7
O3
VCC
A8
A9
A10
O7
O6
O5
O4
CS
O2
12
13
O1
A12
A11
28
4
5
6
7
8
9
10
32 1
27
1314151617
26
25
24
23
22
21
20
11
12
19
O0
Top View
18
NC
A0
A4
A3
A10
NC
CS
A11
O7
O6
7C261
7C263
7C264
7C261
7C263
A7
A2
A1
A12
COLUMN
ADDRESS
ROW
ADDRESS
LCC/PLCC (OpaqueOnly)


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