CY7C344

ALL NEW DESIGNS

Document #: 38-03006 Rev. *B

Page 3 of 15

Timing Delays

Timing delays within the CY7C344 may be easily determined

software. The CY7C344 has fixed internal delays, allowing the

user to determine the worst case timing delays for any design.

Design Recommendations

Operation of the devices described herein with conditions

above those listed under “Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only

and functional operation of the device at these or any other

conditions above those indicated in the operational sections of

this data sheet is not implied. Exposure to absolute maximum

ratings conditions for extended periods of time may affect

device reliability. The CY7C344 contains circuitry to protect

device pins from high-static voltages or electric fields; however,

normal precautions should be taken to avoid applying any

voltage higher than maximum rated voltages.

For proper operation, input and output pins must be

constrained to the range GND

directly at the device. Power supply decoupling capacitors of at least

0.2

Timing Considerations

Unless otherwise stated, propagation delays do not include

expanders. When using expanders, add the maximum

When expander logic is used in the data path, add the appro-

lowest of these frequencies is the maximum data-path frequency for

the synchronous configuration.

When calculating external asynchronous frequencies, use

When expander logic is used in the data path, add the appro-

The lowest of these frequencies is the maximum data-path frequency

for the asynchronous configuration.

when driving other synchronous logic with positive input hold times,

than the minimum required input hold time of the subsequent

synchronous logic, then the devices are guaranteed to function

properly with a common synchronous clock under worst-case

environmental and supply voltage conditions.

device when driving subsequent registered logic with a positive hold

is greater than the minimum required input hold time of the subse-

quent logic (synchronous or asynchronous), then the devices are

guaranteed to function properly under worst-case environmental and

supply voltage conditions, provided the clock signal source is the

same. This also applies if expander logic is used in the clock signal

path of the driving device, but not for the driven device. This is due to

the expander logic in the second device’s clock signal path adding an

device to change prior to the arrival of the clock signal at the following

device’s register.

Figure 1. CY7C344 Timing Model

LOGIC ARRAY

CONTROLDELAY

EXPANDER

DELAY

CLOCK

DELAY

INPUT

DELAY

REGISTER

OUTPUT

DELAY

LOGIC ARRAY

DELAY

FEEDBACK

DELAY

OUTPUT

INPUT

I/O

I/O DELAY

I/O