S,max DC

S

Gate,AVE

V

15V

R

1mA

I

-

=

+

PWM

OSC

OSC

60kHz

f

66.67k

;66.67k

R

2M

R

=

×

W

W <

<

W

DRV110

www.ti.com

SLVSBA8A – MARCH 2012 – REVISED JANUARY 2013

Figure 5. Default frequency is used when OSC is connected to GND directly. PWM frequency as a function of

external fixed adjustment resistor value (greater than 66.67 k

Ω) is given below.

(4)

Figure 5. PWM Clock Frequency Setting

Voltage at the OUT pin, that is the gate voltage of an external switching device, is equal to VIN voltage during

ON-cycle. It is driven to ground during OFF-cycle. VIN voltages below 15 V can be supplied directly from an

external voltage source. Supply voltages of at least 6 V are supported.

regulator that replicates the function of an ideal Zener diode. This requires that the supply current is sufficiently

used to store enough energy to charge the external switch gate capacitance at the OUT pin. Current limiting

resistor size to keep quiescent current less than 1 mA can be calculated by Equation 5.

(5)

Open-drain pull-down path at the STATUS pin is deactivated if either under voltage lockout or thermal shutdown

blocks have triggered.

Copyright © 2012–2013, Texas Instruments Incorporated

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