DRV8804

SLVSAW4C – JULY 2011 – REVISED FEBRUARY 2012

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ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

(1) (2)

VALUE

UNIT

VM

Power supply voltage range

–0.3 to 65

V

VOUTx

Output voltage range

–0.3 to 65

V

VCLAMP

Clamp voltage range

–0.3 to 65

V

SDATOUT,

Output current

20

mA

nFAULT

Peak clamp diode current

2

A

DC or RMS clamp diode current

1

A

Digital input pin voltage range

–0.5 to 7

V

SDATOUT,

Digital output pin voltage range

–0.5 to 7

V

nFAULT

Peak motor drive output current, t < 1

μS

Internally limited

A

Continuous total power dissipation

See Dissipation Ratings table

Operating virtual junction temperature range

–40 to 150

°C

Storage temperature range

–60 to 150

°C

(1)

Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.

(2)

All voltage values are with respect to network ground terminal.

THERMAL INFORMATION

DRV8804

DRV8804

THERMAL METRIC

DW

PWP

UNITS

20 PINS

16 PINS

67.7

39.6

32.9

24.6

35.4

20.3

°C/W

8.2

0.7

34.9

20.1

N/A

2.3

(1)

The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(2)

The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(3)

The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(4)

The junction-to-top characterization parameter,

from the simulation data for obtaining

(5)

The junction-to-board characterization parameter,

from the simulation data for obtaining

(6)

The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

4

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