Summary Tables of Changes

Specification Update

7

Errata

No.

Stepping

Status

Description

D1

D2

1

X

X

No Fix

Audio Pops With High LPC Traffic

2

X

X

No Fix

System Hang With PCIe Upstream Memory Write To FEE00000 With No Data

3

X

X

No Fix

PCIe PLL May Not Power Down In L1 State

4

X

X

No Fix

EHCI Controller—Unable To Mask Wake Events Per Port

5

X

X

No Fix

PCIe Controller Fails To Go Into L1 State In Some Configurations

6

X

X

No Fix

High Definition Audio Does Not Send Interrupts to the CPU using the MSI

7

X

Fixed

Incorrect TPM Access

8

X

Fixed

LPC Prefetch Outside of FWH Region

9

X

X

No Fix

PATA Maximum Slew Rate Specification Violation

10

X

Fixed

USB Client Drops Data Which Causes CRC Errors in Full-Speed Mode

11

X

X

No Fix

System Hang During PCI Configuration Space Access

12

X

Fixed

HD Audio Wall Clock Counter Alias Register

13

X

Fixed

Reads From the HD Audio Wall Clock Counter Return the Same Value

14

X

Plan Fix

SDIO CMD53 Timeout

15

X

Fixed

SDIO Data Buffer Port 20h Read Error

16

X

Fixed

Deadlock Causes Hang Condition Entering L1

17

X

Fixed

Unrecognized USB Device

18

X

Fixed

PCIE PCIHCT WHQL test hang

19

X

X

No Fix

EHCI Controller Hang

20

X

X

No Fix

PCIe Bridge Detects Correctable Errors During Tests

21

X

X

No Fix

HDCTL and FD registers are reset during D3hot to D0 transition

22

X

X

No Fix

23

X

X

No Fix

PCIe Hang Due To Link Disconnect

24

X

No Fix

PCI Express* unaligned memory read that crosses DWORD boundary causes data

corruption

25

X

No Fix

USB Client High Speed termination delay to disconnect D+ pull-up resistor

26

X

No Fix

USB audio device underrun/overrun while performing an isochronous transaction

Specification Changes

No.

SPECIFICATION CHANGES

1

There are no specification changes in this revision of the specification update.

Specification Clarifications

No.

SPECIFICATION CLARIFICATIONS

1

Correction to definition of SDIO bit PSTATE.CSS.