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IDT70V25L15PFG Datasheet(PDF) 11 Page - Integrated Device Technology

Part # IDT70V25L15PFG
Description  HIGH-SPEED 3.3V STATIC RAM
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT70V25L15PFG Datasheet(HTML) 11 Page - Integrated Device Technology

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6.42
11
IDT70V35/34S/L (IDT70V25/24S/L)
High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range for 70V25/24(4)
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM,
CE = VIL, UB or LB = VIL, and SEM = VIH. To access semaphore, CE = VIH or UB & LB = VIH, and SEM = VIL.
4. 'X' in part number indicates power rating (S or L).
70V25/24X15
Com'l Only
70V25/24X20
Com'l
& Ind
70V25/24X25
Com'l
& Ind
Unit
Symbol
Parameter
Min.
Max.Min.Max.Min.Max.
READ CYCLE
tRC
Read Cycle Time
15
____
20
____
25
____
ns
tAA
Address Access Time
____
15
____
20
____
25
ns
tACE
Chip Enable Access Time
(3)
____
15
____
20
____
25
ns
tABE
Byte Enable Access Time(3)
____
15
____
20
____
25
ns
tAOE
Output Enable Access Time(3)
____
10
____
12
____
13
ns
tOH
Output Hold from Address Change
3
____
3
____
3
____
ns
tLZ
Output Low-Z Time(1,2)
3
____
3
____
3
____
ns
tHZ
Output High-Z Time(1,2)
____
10
____
12
____
15
ns
tPU
Chip Enable to Power Up Time(1,2)
0
____
0
____
0
____
ns
tPD
Chip Disable to Power Down Time
(1,2)
____
15
____
20
____
25
ns
tSOP
Semaphore Flag Update Pulse (
OE or SEM)10
____
10
____
10
____
ns
tSAA
Semaphore Address Access(3)
____
15
____
20
____
25
ns
5624 tbl 11a
70V25/24X35
Com'l Only
70V25/24X55
Com'l Only
Unit
Symbol
Parameter
Min.
Max.
Min.
Max.
READ CYCLE
tRC
Read Cycle Time
35
____
55
____
ns
tAA
Address Access Time
____
35
____
55
ns
tACE
Chip Enable Access Time
(3)
____
35
____
55
ns
tABE
Byte Enable Access Time(3)
____
35
____
55
ns
tAOE
Output Enable Access Time(3)
____
20
____
30
ns
tOH
Output Hold from Address Change
3
____
3
____
ns
tLZ
Output Low-Z Time(1,2)
3
____
3
____
ns
tHZ
Output High-Z Time
(1,2)
____
15
____
25
ns
tPU
Chip Enable to Power Up Time(1,2)
0
____
0
____
ns
tPD
Chip Disable to Power Down Time(1,2)
____
35
____
50
ns
tSOP
Semaphore Flag Update Pulse (
OE or SEM)15
____
15
____
ns
tSAA
Semaphore Address Access(3)
____
35
____
55
ns
5624 tbl 11b


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