ADUC824BSZ datasheet(10/68 Pages) AD

Part #	ADUC824BSZ

Description	MicroConverter짰, Dual-Channel 16-/24-Bit ADCs with Embedded FLASH MCU

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REV. B

ADuC824

–10–

12.58 MHz Core_Clk

Variable Core_Clk

Parameter

Min

Max

Min

Max

Unit

Figure

EXTERNAL DATA MEMORY READ CYCLE

tRLRH

RD Pulsewidth

377

6tCORE – 100

ns

4

tAVLL

Address Valid after ALE Low

39

tCORE – 40

ns

4

tLLAX

Address Hold after ALE Low

44

tCORE – 35

ns

4

tRLDV

RD Low to Valid Data In

232

5tCORE – 165

ns

4

tRHDX

Data and Address Hold after

RD

00

ns

4

tRHDZ

Data Float after

RD

89

2tCORE – 70

ns

4

tLLDV

ALE Low to Valid Data In

486

8tCORE – 150

ns

4

tAVDV

Address to Valid Data In

550

9tCORE – 165

ns

4

tLLWL

ALE Low to

RD Low

188

288

3tCORE – 50

3tCORE + 50

ns

4

tAVWL

Address Valid to

RD Low

188

4tCORE – 130

ns

4

tRLAZ

RD Low to Address Float

0

ns

4

tWHLH

RD High to ALE High

39

119

tCORE – 40

tCORE + 40

ns

4

t

LLAX

DATA (IN)

CORE_CLK

ALE (O)

PSEN (O)

PORT 0 (I/O)

PORT 2 (O)

RD (O)

t

LLDV

t

LLWL

t

AVWL

t

AVLL

t

AVDV

t

RLAZ

t

RLDV

t

RHDX

t

RHDZ

t

WHLH

A0–A7

(OUT)

A16–A23

A8–A15

t

RLRH

Figure 4. External Data Memory Read Cycle

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