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AD7569KNZ Datasheet(PDF) 14 Page - Analog Devices |
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AD7569KNZ Datasheet(HTML) 14 Page - Analog Devices |
14 / 20 page –14– REV. B AD7569/AD7669 AD7569/AD7669—ADSP-2100 INTERFACE Figure 19 shows a typical interface to the DSP processor, the ADSP-2100. The ADC is in the Mode 2 interface mode, which means that the ADSP-2100 is halted during conversion. This is achieved using the decoded address output. This is gated with DMWR to ensure that it halts the processor for READ instruc- tions only. INT going low at the end of conversion releases the processor and allows it to finish off the READ instruction. Figure 19. AD7569/AD7669 to ADSP-2100 Interface Because the instruction cycle of the ADSP-2100 is so fast (125 ns cycle), the DMWR pulse also has to be stretched also for write cycles. This is achieved using the 74121, which gener- ates a pulse that is fed back to DMACK. The duration of this pulse determines how long the ADSP-2100 write cycle is stretched. The buffers driving the DMACK line must have open-collector outputs. Writing data to the relevant AD7569/ AD7669 DAC is achieved using a single instruction, <DM (addr) = MRO>, where addr is the decoded address of that DAC, and MRO contains the data to be loaded to the DAC reg- ister. Data is read from the ADC also, using a single instruction <MRO = DM (addr)>, where the conversion result is placed in the MRO data register. AD7569/AD7669—IBM PC* INTERFACE The AD7569/AD7669 is ideal for implementing an analog in- put/output port for the IBM PC. Figure 20 shows an interface that realizes this function. The ADC is configured in the Mode 1 interface mode, and conversions are initiated using a precise clock source for equidistant sampling intervals. At the end of conversion, the INT line goes low, and the 74121 generates Figure 20. AD7569/AD7669 to IBM PC Interface *IBM PC is a trademark of International Business Machines Corp. INTERFACING THE AD7569/AD7669 AD7569/AD7669—Z80 INTERFACE Figure 17 shows a typical interface to the Z80 microprocessor. The ADC is configured for operation in the Mode 1 interface mode. A precise timer or clock source starts conversion in appli- cations requiring equidistant sampling intervals. The scheme used, whereby INT of the AD7569/AD7669 generates an inter- rupt on the Z80, is limited in that it does not allow the ADC to be sampled at the maximum rate. This is because the time be- tween samples has to be long enough to allow the Z80 to service its interrupt and read data from the ADC. To overcome this, some buffer memory or FIFO could be placed between the AD7569/AD7669 and the Z80. Writing data to the relevant AD7569/AD7669 DAC simply consists of a <LD (nn), A> in- struction where nn is the decoded address for that DAC. Read- ing data from the ADC, after an INT has been received, consists of a < LDA, (nn)> instruction. Figure 17. AD7569/AD7669 to Z80 Interface AD7569/AD7669—68008 INTERFACE A typical interface to the 68008 is shown in Figure 18. In this case, the ADC is configured in the Mode 2 interface mode. This means that the one read instruction starts conversion and reads the data. The read cycle is stretched out over the entire conver- sion period by taking the INT line back into the DTACK input of the 68008. The additional gates are required so the 68008 receives a DTACK when the processor is writing data to the AD7569/AD7669. In this case, there are no wait states intro- duced into the write cycle. Writing data to the relevant AD7569/ AD7669 DAC consists of a <MOVE.B Dn, addr> where Dn is the data register, which contains the data to be loaded to that DAC, and addr is the decoded address for the DAC. Data is read from the ADC using a <MOVE.B addr,Dn> with the con- version result placed in register Dn. Figure 18. AD7569/AD7669 to 68008 Interface |
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