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## TPS65320QPWPRQ1 Datasheet(PDF) 13 Page - Texas Instruments

 Part # TPS65320QPWPRQ1 Description 40-V Step-Down Converter With Eco-mode??Codec and LDO Regulator Download 34 Pages Scroll/Zoom 100% Manufacturer TI [Texas Instruments] Direct Link http://www.ti.com Logo

## TPS65320QPWPRQ1 Datasheet(HTML) 13 Page - Texas Instruments

 13 / 34 page05001000150020002500102030405060Input Voltage (V)fsw (Max Skip)fsw (Shift)C012ILOAD = 1AVOUT = 3.3VfSW (Max Skip)fSW (Shift)divLdcoutscdSWONinLhsdf(IRVV )f(shift)t(VIRV )æö æö´++=´ç÷ ç÷-´+èø èøLdcoutdSWONinLhsd(IRVV )1f(max skip)t(VIRV )æö æö´++=´ç÷ ç÷-´+èø èøTPS65320-Q1www.ti.comSLVSAY9A – DECEMBER 2012 – REVISED APRIL 2013Equation 4 is the maximum switching frequency limit set by the frequency-shift protection. To have adequateoutput short-circuit protection at high input voltages, set the switching frequency should be set be less than theƒsw (maxshift) frequency. In Equation 4, to calculate the maximum switching frequency one must take intoaccount that the output voltage decreases from the nominal voltage to 0 volts, and the ƒdiv integer increases from1 to 8 corresponding to the frequency shift.In Figure 15, the solid line illustrates a typical safe operating area regarding frequency shift and assumes theoutput voltage is zero volts, the resistance of the inductor is 0.130Ω, the FET on-resistance is 0.127 Ω, and thediode voltage drop is 0.5 V. The dashed line is the maximum switching frequency to avoid pulse skipping.(3)(4)where:IL = inductor currentRDC = inductor resistanceVIN = maximum input voltageVOUT = output voltageVOUTSC = output voltage during shortVd = diode voltage dropRhs = FET on resistance (typ. 127 mΩ)tON = controllable on-time (typ. 100 ns)ƒdiv = frequency divide factor (equals 1, 2, 4 or 8)Figure 15. Maximum Switching Frequency versus Input VoltageHow to Interface to RT/CLK PinOne can use the RT/CLK pin to synchronize the regulator to an external system clock. To implement thesynchronization feature, connect a square wave to the RT/CLK pin through the circuit network shown inFigure 16. The square-wave amplitude must transition lower than 0.5 V and higher than 2.2 V on the RT/CLK pinand have an on-time greater than 40 ns and an off-time greater than 40 ns. The synchronization frequency rangeis 300 kHz to 2200 kHz. The rising edge of SW is synchronizes with the falling edge of RT/CLK pin signal.Design the external synchronization circuit n such a way that the device has the default frequency-set resistorconnected from the RT/CLK pin to ground should the synchronization signal turn off. TI recommendes using afrequency-set resistor connected as shown in Figure 16 through a 50-Ω resistor to ground. The resistor shouldset the switching frequency close to the external CLK frequency. TI also recommends ac-coupling thesynchronization signal through a 10-pF ceramic capacitor to the RT/CLK pin and a 4-kΩ series resistor. Theseries resistor reduces SW jitter in heavy-load applications when synchronizing to an external clock, and inapplications which transition from synchronizing to RT mode. The first time CLK is pulled above the CLKthreshold, the device switches from the RT resistor frequency to PLL mode. Along with the resulting removal ofCopyright © 2012–2013, Texas Instruments IncorporatedSubmit Documentation Feedback13Product Folder Links: TPS65320-Q1

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