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EVAL-AD7942CBZ1,2 Datasheet(PDF) 6 Page - Analog Devices |
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EVAL-AD7942CBZ1,2 Datasheet(HTML) 6 Page - Analog Devices |
6 / 24 page AD7942 Rev. B | Page 6 of 24 VDD = 2.3 V to 4.5 V1, VIO = 2.3 V to 4.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated, TA = −40°C to +85°C. Table 4. Parameter Symbol Min Typ Max Unit Conversion Time: CNV Rising Edge to Data Available tCONV 0.7 3.2 μs Acquisition Time tACQ 1.8 μs Time Between Conversions tCYC 5 μs CNV Pulse Width (CS Mode) tCNVH 10 ns SCK Period (CS Mode) tSCK 25 ns SCK Period (Chain Mode) tSCK VIO ≥ 3 V 29 ns VIO ≥ 2.7 V 35 ns VIO ≥ 2.3 V 40 ns SCK Low Time tSCKL 12 ns SCK High Time tSCKH 12 ns SCK Falling Edge to Data Remains Valid tHSDO 5 ns SCK Falling Edge to Data Valid Delay tDSDO VIO ≥ 3 V 24 ns VIO ≥ 2.7 V 30 ns VIO ≥ 2.3 V 35 ns CNV or SDI Low to SDO D13 MSB Valid (CS Mode) tEN VIO ≥ 2.7 V 18 ns VIO ≥ 2.3 V 22 ns CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode) tDIS 25 ns SDI Valid Setup Time from CNV Rising Edge (CS Mode) tSSDICNV 30 ns SDI Valid Hold Time from CNV Rising Edge (CS Mode) tHSDICNV 0 ns SCK Valid Setup Time from CNV Rising Edge (Chain Mode) tSSCKCNV 5 ns SCK Valid Hold Time from CNV Rising Edge (Chain Mode) tHSCKCNV 8 ns SDI Valid Setup Time from SCK Falling Edge (Chain Mode) tSSDISCK 5 ns SDI Valid Hold Time from SCK Falling Edge (Chain Mode) tHSDISCK 4 ns SDI High to SDO High (Chain Mode with Busy Indicator) tDSDOSDI 36 ns 1 See Figure 2 and Figure 3 for load conditions. Timing Diagrams 500µA IOL 1.4V TO SDO 500µA IOH CL 50pF Figure 2. Load Circuit for Digital Interface Timing 30% VIO 70% VIO 2V OR VIO – 0.5V1 0.8V OR 0.5V2 0.8V OR 0.5V2 2V OR VIO – 0.5V1 tDELAY tDELAY NOTES 1 2V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V. 2 0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V. Figure 3. Voltage Reference Levels for Timing |
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