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AD5390 Datasheet(PDF) 16 Page - Analog Devices |
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AD5390 Datasheet(HTML) 16 Page - Analog Devices |
16 / 44 page AD5390/AD5391/AD5392 Data Sheet Rev. E | Page 16 of 44 Table 9. Pin Function Descriptions Mnemonic Function VOUT X Buffered Analog Outputs for Channel X. Each analog output is driven by a rail-to-rail output amplifier operating at a gain of 2. Each output is capable of driving an output load of 5 kΩ to ground. Typical output impedance is 0.5 Ω. SIGNAL_GND 1, SIGNAL_GND 2 Analog Ground Reference Points for each group of eight output channels. All SIGNAL_GND pins are tied together internally and should be connected to the AGND plane as close as possible to the AD539x. DAC_GND 1, DAC_GND 2 Each group of eight channels contains a DAC_GND pin. This is the ground reference point for the internal 14-bit DACs. These pins should be connected to the AGND plane. AGND 1, AGND 2 Analog Ground Reference Point. Each group of eight channels contains an AGND pin. All AGND pins should be connected externally to the AGND plane. AVDD 1, AVDD 2 Analog Supply Pins. Each group of eight channels has a separate AVDD pin. These pins should be decoupled with 0.1 uF ceramic capacitors and 10 µF tantalum capacitors. Operating range is 5 V ± 10%. DGND Ground for All Digital Circuitry. DVDD Logic Power Supply. Guaranteed operating range is 2.7 V to 5.5 V. Recommended that these pins be decoupled with 0.1 µF ceramic capacitors and 10 µF tantalum capacitors to DGND. REF_GND Ground Reference Point for the Internal Reference. Connect to AGND. REFOUT/REFIN The AD539x contains a common REFOUT/REFIN pin. When the internal reference is selected, this pin is the reference output. If the application necessitates the use of an external reference, it can be applied to this pin and the internal reference disabled via the control register. The default for this pin is a reference input. MON_OUT Analog Output Pin. When the monitor function is enabled on the AD5390/AD5391, the MON_OUT acts as the output of a 16-to-1 channel multiplexer that can be programmed to multiplex any channel output to the MON_OUT pin. When the monitor function is enabled on the AD5392, the MON_OUT acts as the output of an 8-to-1 channel multiplexer that can be programmed to multiplex any channel output to the MON_OUT pin. The MON_OUT pin output impedance is typically 500 Ω and is intended to drive a high input impedance such as that exhibited by SAR ADC inputs. MON_IN 1, MON_IN 2 Monitor Input Pins. The AD539x contains two monitor input pins to which the user can connect input signals (within the maximum ratings of the device) for monitoring purposes. Any of the signals applied to the MON_IN pins along with the output channels can be switched to the MON_OUT pin via software. An external ADC, for example, can be used to monitor these signals. SYNC/AD0 Serial Interface Pin. This is the frame synchronization input signal for the serial interface. When taken low, the internal counter is enabled to count the required number of clocks before the addressed register is updated. In I2C mode, AD0 acts as a hardware address pin. DCEN/AD1 Interface Control Pin. Operation is determined by the interface select bit SPI/I2C. Serial Interface Mode: Daisy-Chain Select Input (level-sensitive, active high). When high, this pin enables daisy-chain operation to allow a number of devices to be cascaded together. I2C Mode: This pin acts as a hardware address pin used in conjunction with AD0 to determine the software address for this device on the I2C bus. SDO Serial Data Output. Three-state CMOS output. SDO can be used for daisy-chaining a number of devices together. Data is clocked out on SDO on the rising edge of SCLK and is valid on the falling edge of SCLK. BUSY Digital CMOS Output. BUSY goes low during internal calculations of the data (x2) loaded to the DAC data register. During this time, the user can continue writing new data to further the x1, c, and m registers (these are stored in a FIFO), but no further updates to the DAC registers and DAC outputs can take place. If LDAC is taken low while BUSY is low, this event is stored. BUSY also goes low during power-on reset and when the RESET pin is low. During this time the interface is disabled and any events on LDAC are ignored. A CLR operation also brings BUSY low. LDAC Load DAC Logic Input (active low). If LDAC is taken low while BUSY is inactive (high), the contents of the input registers are transferred to the DAC registers and the DAC outputs are updated. If LDAC is taken low while BUSY is active and internal calculations are taking place, the LDAC event is stored and the DAC registers are updated when BUSY goes inactive. However, any events on LDAC during power-on reset or RESET are ignored. CLR Asynchronous Clear Input. The CLR input is falling edge sensitive. While CLR is low, all LDAC pulses are ignored. When CLR is activated, all channels are updated with the data contained in the CLR code register. BUSY is low for a duration of 20 µs (AD5390/AD5391) and 15 µs (AD5392) while all channels are being updated with the CLR code. RESET Asynchronous Digital Reset Input (falling edge sensitive). The function of this pin is equivalent to that of the power-on reset generator. When this pin is taken low, the state machine initiates a reset sequence to digitally reset the x1, m, c, and x2 registers to their default power-on values. This sequence takes 270 µs maximum. This falling edge of RESET initiates the RESET process and BUSY goes low for the duration, returning high when RESET is complete. While BUSY is low, all interfaces are disabled and all LDAC pulses are ignored. When BUSY returns high, the part resumes normal operation and the status of the RESET pin is ignored until the next falling edge is detected. |
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Similar Description - AD5390_12 |
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