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AD5320 Datasheet(PDF) 6 Page - Analog Devices

Part # AD5320
Description  2.7 V to 5.5 V, 140 關A, Rail-to-Rail Output 12-Bit DAC in an SOT-23
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD5320 Datasheet(HTML) 6 Page - Analog Devices

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AD5320
Rev. C | Page 6 of 20
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
AD5320
TOP VIEW
(Not to Scale)
VOUT 1
GND 2
VDD 3
SYNC
SCLK
DIN
6
5
4
Figure 3. SOT-23 Pin Configuration
AD5320
TOP VIEW
(Not to Scale)
VDD 1
NC 2
NC 3
VOUT 4
SYNC
SCLK
DIN
GND
8
7
6
5
NC = NO CONNECT
Figure 4. MSOP Pin Configuration
Table 4. Pin Function Descriptions
SOT-23
Pin No.
MSOP
Pin No.
Mnemonic
Description
1
4
VOUT
Analog Output Voltage from DAC. The output amplifier has rail-to-rail operation.
2
8
GND
Ground Reference Point for All Circuitry on the Part.
3
1
VDD
Power Supply Input. These parts can be operated from 2.5 V to 5.5 V and VDD should be decoupled
to GND.
4
7
DIN
Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling
edge of the serial clock input.
5
6
SCLK
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock
input. Data can be transferred at rates up to 30 MHz.
6
5
SYNC
Level Triggered Control Input (Active Low). This is the frame synchronization signal for the input data.
When SYNC goes low, it enables the input shift register and data is transferred in on the falling edges
of the following clocks. The DAC is updated following the 16th clock cycle unless SYNC is taken high
before this edge, in which case the rising edge of SYNC acts as an interrupt and the write sequence is
ignored by the DAC.
2, 3
NC
No Connect.


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