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X28HC256PZ-90 Datasheet(PDF) 8 Page - Rochester Electronics |
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X28HC256PZ-90 Datasheet(HTML) 8 Page - Rochester Electronics |
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8 / 21 page  7 FN8108.2 May 7, 2007 The Toggle Bit I/O6 ¬ The Toggle Bit can eliminate the chore of saving and fetching the last address and data in order to implement DATA Polling. This can be especially helpful in an array comprised of multiple X28HC256 memories that is frequently updated. The timing diagram in Figure 4 illustrates the sequence of events on the bus. The software flow diagram in Figure 5 illustrates a method for polling the Toggle Bit. Hardware Data Protection The X28HC256 provides two hardware features that protect nonvolatile data from inadvertent writes. • Default VCC Sense—All write functions are inhibited when VCC is 3.5V typically. • Write Inhibit—Holding either OE LOW, WE HIGH, or CE HIGH will prevent an inadvertent write cycle during power- up and power-down, maintaining data integrity. Software Data Protection The X28HC256 offers a software-controlled data protection feature. The X28HC256 is shipped from Intersil with the software data protection NOT ENABLED; that is, the device will be in the standard operating mode. In this mode data should be protected during power-up/down operations through the use of external circuits. The host would then have open read and write access of the device once VCC was stable. The X28HC256 can be automatically protected during power-up and power-down (without the need for external circuits) by employing the software data protection feature. The internal software data protection circuit is enabled after the first write operation, utilizing the software algorithm. This circuit is nonvolatile, and will remain set for the life of the device unless the reset command is issued. Once the software protection is enabled, the X28HC256 is also protected from inadvertent and accidental writes in the powered-up state. That is, the software algorithm must be issued prior to writing additional data to the device. CE OE WE X28C512, X28C513 LAST WRITE I/O6 HIGH Z * * VOH VOL READY * I/O6 Beginning and ending state of I/O6 will vary. FIGURE 4. TOGGLE BIT BUS SEQUENCE COMPARE X28C256 NO YES OK? COMPARE ACCUM WITH ADDR n LOAD ACCUM FROM ADDR n LAST WRITE READY YES FIGURE 5. TOGGLE BIT SOFTWARE FLOW X28HC256 |
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