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MCF5272VM66 Datasheet(PDF) 5 Page - Freescale Semiconductor, Inc
FREESCALE [Freescale Semiconductor, Inc]
MCF5272VM66 Datasheet(HTML) 5 Page - Freescale Semiconductor, Inc
/ 12 page
MCF5272 Integrated Microprocessor Product Brief
decrement and branch, integer division, and integer multiply with a 64-bit result. Also, four indirect
addressing modes have been eliminated.
The ColdFire 2 core incorporates a complete debug module that provides real-time trace, background debug
mode, and real-time debug support.
System Integration Module (SIM)
The MCF5272 SIM provides the external bus interface for the ColdFire 2 architecture. It also eliminates
most or all of the glue logic that typically supports the microprocessor and its interface with the peripheral
and memory system. The SIM provides programmable circuits to perform address-decoding and chip
selects, wait-state insertion, interrupt handling, clock generation, discrete I/O, and power management
External Bus Interface
The external bus interface (EBI) handles the transfer of information between the internal core and memory,
peripherals, or other processing elements in the external address space.
Chip Select and Wait State Generation
Programmable chip select outputs provide signals to enable external memory and peripheral circuits,
providing all handshaking and timing signals for automatic wait-state insertion and data bus sizing.
Base memory address and block size are programmable, with some restrictions. For example, the starting
address must be on a boundary that is a multiple of the block size. Each chip select is general purpose;
however, any one of the chip selects can be programmed to provide read and write enable signals suitable
for use with most popular static RAMs and peripherals. Data bus width (8-bit, 16-bit, or 32-bit) is
programmable on all chip selects, and further decoding is available for protection from user mode access or
System Conﬁguration and Protection
The SIM provides conﬁguration registers that allow general system functions to be controlled and
monitored. For example, all on-chip registers can be relocated as a block by programming a module base
address, power management modes can be selected, and the source of the most recent RESET or BERR can
be checked. The hardware watchdog features can be enabled or disabled, and the bus time-out period can
A software watchdog timer is also provided for system protection. If programmed, the timer causes a reset
to the MCF5272 if it is not refreshed periodically by software.
The sleep and stop power management modes reduce power consumption by allowing software to shut
down the core, peripherals, or the whole device during inactive periods. To reduce power consumption
further, software can individually disable internal clocks to the on-chip peripheral modules. The
power-saving modes are described as follows:
Sleep mode uses interrupt control logic to allow any interrupt condition to wake the processor. As
the MCF5272 is fully static, sleep mode is simply the disabling of the core’s clock after the current
instruction completes. An interrupt from any internal or external source causes on-chip power
Freescale Semiconductor, Inc.
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