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MCF5272VM66 Datasheet(PDF) 4 Page - Freescale Semiconductor, Inc

Part No. MCF5272VM66
Description  This document provides an overview of the MCF5272 microprocessor features, including the major functional components.
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Maker  FREESCALE [Freescale Semiconductor, Inc]
Homepage  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MCF5272VM66 Datasheet(HTML) 4 Page - Freescale Semiconductor, Inc

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MCF5272 Integrated Microprocessor Product Brief
MOTOROLA
MCF5272 Architecture
— Versatile programmable chip select signals with wait state generation logic
— Up to three 16-bit parallel input/output ports
— Latchable interrupt inputs with programmable priority and edge triggering
— Programmable interrupt vectors for on-chip peripherals
Physical layer interface controller (PLIC)
— Allows connection using general circuit interface (GCI) or interchip digital link (IDL)
physical layer protocols for 2B + D data
— Three physical interfaces
— Four time-division multiplex (TDM) ports
IEEE 1149.1 boundary-scan test access port (JTAG) for board-level testing
Operating voltage: 3.3 V ±0.3 V
Operating temperature: 0°–70°C
Operating frequency: DC to 66 MHz, from external CMOS oscillator
Compact ultra low-profile 196 ball-molded plastic ball-grid array package (PGBA)
1.2
MCF5272 Architecture
This section briefly describes the MCF5272 core, SIM, UART, and timer modules, and test access port.
1.2.1
Version 2 ColdFire Core
Based on the concept of variable-length RISC technology, ColdFire combines the simplicity of conventional
32-bit RISC architectures with a memory-saving, variable-length instruction set. The main features of the
MCF5272 core are as follows:
32-bit address bus directly addresses up to 4 Gbytes of address space
32-bit data bus
Variable-length RISC
Optimized instruction set for high-level language constructs
Sixteen general-purpose 32-bit data and address registers
MAC unit for DSP applications
Supervisor/user modes for system protection
Vector base register to relocate exception-vector table
Special core interfacing signals for integrated memories
Full debug support
The Version 2 ColdFire core has a 32-bit address bus and a 32-bit data bus. The address bus allows direct
addressing of up to 4 Gbytes. It supports misaligned data accesses and a bus arbitration unit for multiple bus
masters.
The Version 2 ColdFire supports an enhanced subset of the 68000 instruction set. The MAC provides new
instructions for DSP applications; otherwise, Version 2 ColdFire user code runs unchanged on 68020,
68030, 68040, and 68060 processors. The removed instructions include BCD, bit field, logical rotate,
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com


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