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FM33256B Datasheet(PDF) 9 Page - Cypress Semiconductor |
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FM33256B Datasheet(HTML) 9 Page - Cypress Semiconductor |
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9 / 30 page  FM33256B SPI Companion w/ FRAM Document Number: 001-86213 Rev. ** Page 9 of 30 Figure 9. Real-time Clock Core Block Diagram Backup Power The real-time clock/calendar is intended to be permanently powered. When the primary system power fails, the voltage on the VDD pin will drop. When VDD is less 2.5V, the RTC (and event counters) will switch to the backup power supply on VBAK. The clock operates at extremely low current in order to maximize battery or capacitor life. However, an advantage of combining a clock function with FRAM memory is that data is not lost regardless of the backup power source. The IBAK current varies with temperature and voltage (see DC parametric table). Figure 10 shows IBAK as a function of VBAK. These curves are useful for calculating backup time when a capacitor is used as the VBAK source. The minimum VBAK voltage varies linearly with temperature. The user can expect the minimum VBAK voltage to be 1.23V at +85°C and 1.90V at -40°C. The tested limit is 1.55V at +25°C. Figure 10. IBAK vs. VBAK Voltage Figure 11. VBAK (min.) vs Temperature Note: The minimum VBAK voltage has been characterized at -40°C and +85°C but is not 100% tested. 32.768 kHz crystal Oscillator Clock Divider Update Logic 512 Hz or SW out W R Seconds 7 bits Minutes 7 bits Hours 6 bits Date 6 bits Months 5 bits Years 8 bits CF Days 3 bits User Registers 1 Hz /OSCEN |
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