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CYUSB3031-BZXC Datasheet(PDF) 11 Page - Cypress Semiconductor |
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CYUSB3031-BZXC Datasheet(HTML) 11 Page - Cypress Semiconductor |
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11 / 50 page  CYUSB3035 Document Number: 001-84160 Rev. *B Page 11 of 50 32-kHz Watchdog Timer Clock Input FX3S includes a watchdog timer. The watchdog timer can be used to interrupt the ARM926EJ-S core, automatically wake up the FX3S in Standby mode, and reset the ARM926EJ-S core. The watchdog timer runs a 32-kHz clock, which may be optionally supplied from an external source on a dedicated FX3S pin. The firmware can disable the watchdog timer. Requirements for the optional 32-kHz clock input are listed in Table 5. Power FX3S has the following power supply domains: ■ IO_VDDQ: This is a group of independent supply domains for digital I/Os. The voltage level on these supplies is 1.8 V to 3.3 V. FX3S provides six independent supply domains for digital I/Os listed as follows (see Pin Description on page 16 for details on each of the power domain signals): ❐ VIO1: GPIF II I/O ❐ VIO2: S0-Port Supply ❐ VIO3: S1-Port Supply ❐ VIO4: S1-Port and Low Speed Peripherals (UART/SPI/I2S) Supply ❐ VIO5: I2C and JTAG (supports 1.2 V to 3.3 V) ❐ CVDDQ: Clock ❐ VDD: This is the supply voltage for the logic core. The nominal supply-voltage level is 1.2 V. This supplies the core logic circuits. The same supply must also be used for the following: • AVDD: This is the 1.2-V supply for the PLL, crystal oscilla- tor, and other core analog circuits • U3TXVDDQ/U3RXVDDQ: These are the 1.2-V supply volt- ages for the USB 3.0 interface. ■ VBATT/VBUS: This is the 3.2-V to 6-V battery power supply for the USB I/O and analog circuits. This supply powers the USB transceiver through FX3S's internal voltage regulator. VBATT is internally regulated to 3.3 V. Table 4. FX3S Input Clock Specifications Parameter Description Specification Units Min Max Phase noise 100-Hz offset – –75 dB 1- kHz offset – –104 dB 10-kHz offset – –120 dB 100-kHz offset – –128 dB 1-MHz offset – –130 dB Maximum frequency deviation – 150 ppm Duty cycle 30 70 % Overshoot – 3 % Undershoot – –3 % Rise time/fall time – 3 ns Table 5. 32-kHz Clock Input Requirements Parameter Min Max Units Duty cycle 40 60 % Frequency deviation – ±200 ppm Rise time/fall time – 200 ns |
Similar Part No. - CYUSB3031-BZXC |
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