CYRF8935

Document Number: 001-61351 Rev. *J

Page 7 of 40

The following sections show the detailed timing diagrams. All timing diagrams show active high for PKT and FIFO flags. Active low is

also available through register 41[10] setting.

Framer: Packet Length Handling

The CYRF8935 framer handles packet length by setting register

41[13] = 1. The first byte of the payload is regarded as packet

length (this length byte is not counted in the packet length). The

CYRF8935 supports packet lengths up to 255 bytes. The framer

handles Tx/Rx start and stop.

Transmit Timing

The Tx timing diagram is shown in Figure 5. After MCU writes

register 7[8]= TX_EN = 1, the framer automatically generates the

Tx packet using payload data from the FIFO register. The

frequency (RF channel) will be as specified in register 7 at the

time TX_EN is written to 1.

The MCU or application must load transmit data into the FIFO

register before the framer sends trailer bits. You can do this by

loading the transmit payload data into the FIFO register either

before or after writing TX_EN = 1. For slower applications, it is

easier to load the FIFO register, and then write TX_EN = 1. For

the higher frame rate (faster) applications, write register 7

TX_EN = 1, and then load the FIFO register with payload data

during the Tx on delay time, as shown in Figure 5.

If the packet length exceeds the FIFO length, the MCU must

write FIFO data multiple times. The FIFO flag indicates whether

FIFO is empty in transmit state.

Figure 5. Tx Timing Diagram when Register 41[13] = 1 (Framer Handles Packet Length)

PKT and FIFO Flags are Active High

Table 3. CYRF8935 Configuration for Packet Length

Register 41[13]

PACK_LENGTH_EN

Register 41[12]

FW_TERM_TX

CYRF8935 Framer Start/Stop

0

(MCU or application handles

packet length)

0

Transmit stops only when Register 7 TX_EN = 0.

See FW_TERM_TX = 0 (Transmit) on page 10 for details.

Receive stops only when Register 7 RX_EN = 0.

See FW_TERM_TX= 0 (Receive) on page 11 for details.

1

Transmit automatically stops whenever FIFO runs empty.

Receive stops only when Register 7 RX_EN = 0.

See Receive Timing on page 8.

1

(CYRF8935 framer handles

packet length)

x

(do not care)

The first byte of payload is regarded as packet length, 0 to 255 bytes.

Transmit automatically stops when all 0 to 255 bytes are transmitted.

See Framer: Packet Length Handling on page 7 for details.

SPI_SS

Internal

Tx On

2 µs

Tx On Delay

PA Ramp Up

Tx Packet

Transmit Data

Write Reg. 7

FIFO

MCU fills FIFO before framer sends trailer bits.

PKT = 1 after Tx packet has been sent.

FIFO = 1 when FIFO is empty

PKT