CY14MC256J

CY14MB256J

CY14ME256J

Document Number: 001-65233 Rev. *G

Page 3 of 30

Pinouts

Figure 1. 8-pin SOIC pinout [3]

Figure 2. 16-pin SOIC pinout

WP

SCL

1

2

3

4

5

A0

8

7

6

V

CC

SDA

A1

A2

V

Top View

not to scale

CY14MX256J1

SS

WP

SCL

1

2

3

4

5

8

7

6

V

CC

SDA

A1

A2

Top View

not to scale

CY14MX256J2

V

CAP

VSS

WP

V

CAP

1

2

3

4

5

6

7

8

9

10

11

12

13

NC

16

15

14

VCC

A2

SDA

SCL

A1

HSB

A0

Top View

not to scale

VSS

NC

NC

NC

NC

NC

CY14MX256J3

Pin Definitions

Pin Name

I/O Type

Description

SCL

Input

SDA

Output: Is open-drain and requires an external pull-up resistor.

WP

Input

Write Protect. Protects the memory from all writes. This pin is internally pulled LOW and hence can be

left open if not connected.

A2–A0 [3]

Input

left open if not connected.

HSB

Input/Output Hardware STORE Busy

Output: Indicates busy status of nvSRAM when LOW. After each Hardware and Software STORE

weak internal pull-up resistor keeps this pin HIGH (External pull up resistor connection optional).

Input: Hardware STORE implemented by pulling this pin LOW externally.

Power supply AutoStore capacitor. Supplies power to the nvSRAM during power loss to STORE data from the SRAM

to nonvolatile elements. If not required, AutoStore must be disabled and this pin left as no connect. It

must never be connected to ground.

NC

No connect

No connect. This pin is not connected to the die.

Power supply Ground.

Power supply Power supply.

Note

3. A0 pin is not available in CY14MX256J2.